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Commit 36c0d0cf authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: s/_TRANSA_CHICKEN/TRANS_CHICKEN(PIPE_A)/ 



Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent eede3b53

drivers/gpu/drm/i915/intel_display.c

+4 −4
Original line number Original line Diff line number Diff line
@@ -2050,9 +2050,9 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, 
	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);

	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);





	/* Workaround: set timing override bit. */

	/* Workaround: set timing override bit. */

	val = I915_READ(_TRANSA_CHICKEN2);

	val = I915_READ(TRANS_CHICKEN2(PIPE_A));

	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;

	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;

	I915_WRITE(_TRANSA_CHICKEN2, val);

	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);





	val = TRANS_ENABLE;

	val = TRANS_ENABLE;

	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));

	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
@@ -2110,9 +2110,9 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) 
		DRM_ERROR("Failed to disable PCH transcoder\n");

		DRM_ERROR("Failed to disable PCH transcoder\n");





	/* Workaround: clear timing override bit. */

	/* Workaround: clear timing override bit. */

	val = I915_READ(_TRANSA_CHICKEN2);

	val = I915_READ(TRANS_CHICKEN2(PIPE_A));

	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;

	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;

	I915_WRITE(_TRANSA_CHICKEN2, val);

	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);

}

}





/**

/**

drivers/gpu/drm/i915/intel_pm.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -6640,8 +6640,8 @@ static void lpt_init_clock_gating(struct drm_device *dev) 
			   PCH_LP_PARTITION_LEVEL_DISABLE);

			   PCH_LP_PARTITION_LEVEL_DISABLE);





	/* WADPOClockGatingDisable:hsw */

	/* WADPOClockGatingDisable:hsw */

	I915_WRITE(_TRANSA_CHICKEN1,

	I915_WRITE(TRANS_CHICKEN1(PIPE_A),

		   I915_READ(_TRANSA_CHICKEN1) |

		   I915_READ(TRANS_CHICKEN1(PIPE_A)) |

		   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);

		   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);

}

}