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Commit 93442184 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx8: use cached values for raster config in clear state 



Use the cached values rather than hardcoding it.

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 671b00e2

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+2 −31
Original line number Diff line number Diff line
@@ -4313,37 +4313,8 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev) 


	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));

	amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);

	switch (adev->asic_type) {

	case CHIP_TONGA:

	case CHIP_POLARIS10:

		amdgpu_ring_write(ring, 0x16000012);

		amdgpu_ring_write(ring, 0x0000002A);

		break;

	case CHIP_POLARIS11:

	case CHIP_POLARIS12:

		amdgpu_ring_write(ring, 0x16000012);

		amdgpu_ring_write(ring, 0x00000000);

		break;

	case CHIP_FIJI:

		amdgpu_ring_write(ring, 0x3a00161a);

		amdgpu_ring_write(ring, 0x0000002e);

		break;

	case CHIP_CARRIZO:

		amdgpu_ring_write(ring, 0x00000002);

		amdgpu_ring_write(ring, 0x00000000);

		break;

	case CHIP_TOPAZ:

		amdgpu_ring_write(ring, adev->gfx.config.num_rbs == 1 ?

				0x00000000 : 0x00000002);

		amdgpu_ring_write(ring, 0x00000000);

		break;

	case CHIP_STONEY:

		amdgpu_ring_write(ring, 0x00000000);

		amdgpu_ring_write(ring, 0x00000000);

		break;

	default:

		BUG();

	}

	amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);

	amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);



	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

	amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);