Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9326011e authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'x86/cleanups' into x86/cpu, to pick up dependent changes 



Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents 77e5517c 32b1cbe3

arch/x86/include/asm/bitops.h

+3 −4
Original line number Diff line number Diff line
@@ -45,14 +45,13 @@ 
 * We do the locked ops that don't return the old value as

 * a mask operation on a byte.

 */

#define IS_IMMEDIATE(nr)		(__builtin_constant_p(nr))

#define CONST_MASK_ADDR(nr, addr)	WBYTE_ADDR((void *)(addr) + ((nr)>>3))

#define CONST_MASK(nr)			(1 << ((nr) & 7))



static __always_inline void

arch_set_bit(long nr, volatile unsigned long *addr)

{

	if (IS_IMMEDIATE(nr)) {

	if (__builtin_constant_p(nr)) {

		asm volatile(LOCK_PREFIX "orb %1,%0"

			: CONST_MASK_ADDR(nr, addr)

			: "iq" ((u8)CONST_MASK(nr))
@@ -72,7 +71,7 @@ arch___set_bit(long nr, volatile unsigned long *addr) 
static __always_inline void

arch_clear_bit(long nr, volatile unsigned long *addr)

{

	if (IS_IMMEDIATE(nr)) {

	if (__builtin_constant_p(nr)) {

		asm volatile(LOCK_PREFIX "andb %1,%0"

			: CONST_MASK_ADDR(nr, addr)

			: "iq" ((u8)~CONST_MASK(nr)));
@@ -123,7 +122,7 @@ arch___change_bit(long nr, volatile unsigned long *addr) 
static __always_inline void

arch_change_bit(long nr, volatile unsigned long *addr)

{

	if (IS_IMMEDIATE(nr)) {

	if (__builtin_constant_p(nr)) {

		asm volatile(LOCK_PREFIX "xorb %1,%0"

			: CONST_MASK_ADDR(nr, addr)

			: "iq" ((u8)CONST_MASK(nr)));

arch/x86/include/asm/cpufeature.h

+7 −0
Original line number Diff line number Diff line
@@ -61,6 +61,13 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; 
#define CHECK_BIT_IN_MASK_WORD(maskname, word, bit)	\

	(((bit)>>5)==(word) && (1UL<<((bit)&31) & maskname##word ))



/*

 * {REQUIRED,DISABLED}_MASK_CHECK below may seem duplicated with the

 * following BUILD_BUG_ON_ZERO() check but when NCAPINTS gets changed, all

 * header macros which use NCAPINTS need to be changed. The duplicated macro

 * use causes the compiler to issue errors for all headers so that all usage

 * sites can be corrected.

 */

#define REQUIRED_MASK_BIT_SET(feature_bit)		\

	 ( CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK,  0, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK,  1, feature_bit) ||	\

arch/x86/include/asm/realmode.h

+0 −1
Original line number Diff line number Diff line
@@ -20,7 +20,6 @@ struct real_mode_header { 
	u32	ro_end;

	/* SMP trampoline */

	u32	trampoline_start;

	u32	trampoline_status;

	u32	trampoline_header;

#ifdef CONFIG_X86_64

	u32	trampoline_pgd;

arch/x86/include/asm/text-patching.h

+2 −2
Original line number Diff line number Diff line
@@ -45,8 +45,8 @@ extern void text_poke_early(void *addr, const void *opcode, size_t len); 
 * no thread can be preempted in the instructions being modified (no iret to an

 * invalid instruction possible) or if the instructions are changed from a

 * consistent state to another consistent state atomically.

 * On the local CPU you need to be protected again NMI or MCE handlers seeing an

 * inconsistent instruction while you patch.

 * On the local CPU you need to be protected against NMI or MCE handlers seeing

 * an inconsistent instruction while you patch.

 */

extern void *text_poke(void *addr, const void *opcode, size_t len);

extern void *text_poke_kgdb(void *addr, const void *opcode, size_t len);

arch/x86/kernel/alternative.c

+3 −3
Original line number Diff line number Diff line
@@ -713,7 +713,7 @@ void __init alternative_instructions(void) 
	 * Don't stop machine check exceptions while patching.

	 * MCEs only happen when something got corrupted and in this

	 * case we must do something about the corruption.

	 * Ignoring it is worse than a unlikely patching race.

	 * Ignoring it is worse than an unlikely patching race.

	 * Also machine checks tend to be broadcast and if one CPU

	 * goes into machine check the others follow quickly, so we don't

	 * expect a machine check to cause undue problems during to code
@@ -753,8 +753,8 @@ void __init alternative_instructions(void) 
 * When you use this code to patch more than one byte of an instruction

 * you need to make sure that other CPUs cannot execute this code in parallel.

 * Also no thread must be currently preempted in the middle of these

 * instructions. And on the local CPU you need to be protected again NMI or MCE

 * handlers seeing an inconsistent instruction while you patch.

 * instructions. And on the local CPU you need to be protected against NMI or

 * MCE handlers seeing an inconsistent instruction while you patch.

 */

void __init_or_module text_poke_early(void *addr, const void *opcode,

				      size_t len)