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Commit 9220d7be authored by Boris Brezillon's avatar Boris Brezillon
Browse files

Merge tag 'nand/for-5.1' of git://git.infradead.org/linux-mtd into mtd/next 

NAND core changes:
- Fourth batch of fixes/cleanup to the raw NAND core impacting various
  controller drivers (Sunxi, Marvell, MTK, TMIO, OMAP2).
- Checking the return code of nand_reset() and nand_readid_op().
- Removing ->legacy.erase and single_erase().
- Simplifying the locking.
- Several implicit fall through annotations.

Raw NAND controllers drivers changes:
- Fixing various possible object reference leaks (MTK, JZ4780, Atmel).
- ST:
  * Adding support for STM32 FMC2 NAND flash controller.
- Meson:
  * Adding support for Amlogic NAND flash controller.
- Denali:
  * Several cleanup patches.
- Sunxi:
  * Several cleanup patches.
- FSMC:
  * Disabling NAND on remove().
  * Resetting NAND timings on resume().

SPI-NAND drivers changes:
- Toshiba:
  * Adding support for all Toshiba products.
- Macronix:
  * Fixing ECC status read.
- Gigadevice:
  * Adding support for GD5F1GQ4UExxG.
parents dfbd3995 53bcbb83

Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt

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Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs



This file documents the properties in addition to those available in

the MTD NAND bindings.



Required properties:

- compatible : contains one of:

  - "amlogic,meson-gxl-nfc"

  - "amlogic,meson-axg-nfc"

- clocks     :

	A list of phandle + clock-specifier pairs for the clocks listed

	in clock-names.



- clock-names: Should contain the following:

	"core" - NFC module gate clock

	"device" - device clock from eMMC sub clock controller

	"rx" - rx clock phase

	"tx" - tx clock phase



- amlogic,mmc-syscon	: Required for NAND clocks, it's shared with SD/eMMC

				controller port C



Optional children nodes:

Children nodes represent the available nand chips.



Other properties:

see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.



Example demonstrate on AXG SoC:



	sd_emmc_c_clkc: mmc@7000 {

		compatible = "amlogic,meson-axg-mmc-clkc", "syscon";

		reg = <0x0 0x7000 0x0 0x800>;

	};



	nand-controller@7800 {

		compatible = "amlogic,meson-axg-nfc";

		reg = <0x0 0x7800 0x0 0x100>;

		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;



		clocks = <&clkc CLKID_SD_EMMC_C>,

			<&sd_emmc_c_clkc CLKID_MMC_DIV>,

			<&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>,

			<&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>;

		clock-names = "core", "device", "rx", "tx";

		amlogic,mmc-syscon = <&sd_emmc_c_clkc>;



		pinctrl-names = "default";

		pinctrl-0 = <&nand_pins>;



		nand@0 {

			reg = <0>;

			#address-cells = <1>;

			#size-cells = <1>;



			nand-on-flash-bbt;

		};

	};

Documentation/devicetree/bindings/mtd/stm32-fmc2-nand.txt

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STMicroelectronics Flexible Memory Controller 2 (FMC2)

NAND Interface



Required properties:

- compatible: Should be one of:

              * st,stm32mp15-fmc2

- reg: NAND flash controller memory areas.

       First region contains the register location.

       Regions 2 to 4 respectively contain the data, command,

       and address space for CS0.

       Regions 5 to 7 contain the same areas for CS1.

- interrupts: The interrupt number

- pinctrl-0: Standard Pinctrl phandle (see: pinctrl/pinctrl-bindings.txt)

- clocks: The clock needed by the NAND flash controller



Optional properties:

- resets: Reference to a reset controller asserting the FMC controller

- dmas: DMA specifiers (see: dma/stm32-mdma.txt)

- dma-names: Must be "tx", "rx" and "ecc"



* NAND device bindings:



Required properties:

- reg: describes the CS lines assigned to the NAND device.



Optional properties:

- nand-on-flash-bbt: see nand.txt

- nand-ecc-strength: see nand.txt

- nand-ecc-step-size: see nand.txt



The following ECC strength and step size are currently supported:

 - nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Hamming)

 - nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4)

 - nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8) (default)



Example:



	fmc: nand-controller@58002000 {

		compatible = "st,stm32mp15-fmc2";

		reg = <0x58002000 0x1000>,

		      <0x80000000 0x1000>,

		      <0x88010000 0x1000>,

		      <0x88020000 0x1000>,

		      <0x81000000 0x1000>,

		      <0x89010000 0x1000>,

		      <0x89020000 0x1000>;

		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&rcc FMC_K>;

		resets = <&rcc FMC_R>;

		pinctrl-names = "default";

		pinctrl-0 = <&fmc_pins_a>;

		#address-cells = <1>;

		#size-cells = <0>;



		nand@0 {

			reg = <0>;

			nand-on-flash-bbt;

			#address-cells = <1>;

			#size-cells = <1>;

		};

	};

MAINTAINERS

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@@ -9849,6 +9849,13 @@ F: drivers/media/platform/meson/ao-cec.c 
F:	Documentation/devicetree/bindings/media/meson-ao-cec.txt

T:	git git://linuxtv.org/media_tree.git



MESON NAND CONTROLLER DRIVER FOR AMLOGIC SOCS

M:	Liang Yang <liang.yang@amlogic.com>

L:	linux-mtd@lists.infradead.org

S:	Maintained

F:	drivers/mtd/nand/raw/meson_*

F:	Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt



MICROBLAZE ARCHITECTURE

M:	Michal Simek <monstr@monstr.eu>

W:	http://www.monstr.eu/fdt/

drivers/mtd/nand/raw/Kconfig

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@@ -541,4 +541,21 @@ config MTD_NAND_TEGRA 
	  is supported. Extra OOB bytes when using HW ECC are currently

	  not supported.



config MTD_NAND_STM32_FMC2

	tristate "Support for NAND controller on STM32MP SoCs"

	depends on MACH_STM32MP157 || COMPILE_TEST

	help

	  Enables support for NAND Flash chips on SoCs containing the FMC2

	  NAND controller. This controller is found on STM32MP SoCs.

	  The controller supports a maximum 8k page size and supports

	  a maximum 8-bit correction error per sector of 512 bytes.



config MTD_NAND_MESON

	tristate "Support for NAND controller on Amlogic's Meson SoCs"

	depends on ARCH_MESON || COMPILE_TEST

	select MFD_SYSCON

	help

	  Enables support for NAND controller on Amlogic's Meson SoCs.

	  This controller is found on Meson SoCs.



endif # MTD_NAND

drivers/mtd/nand/raw/Makefile

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@@ -56,6 +56,8 @@ obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ 
obj-$(CONFIG_MTD_NAND_QCOM)		+= qcom_nandc.o

obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_ecc.o mtk_nand.o

obj-$(CONFIG_MTD_NAND_TEGRA)		+= tegra_nand.o

obj-$(CONFIG_MTD_NAND_STM32_FMC2)	+= stm32_fmc2_nand.o

obj-$(CONFIG_MTD_NAND_MESON)		+= meson_nand.o



nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o

nand-objs += nand_onfi.o