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Commit dfbd3995 authored by Boris Brezillon's avatar Boris Brezillon
Browse files

Merge tag 'spi-nor/for-5.1' of git://git.infradead.org/linux-mtd into mtd/next

SPI NOR Changes
  Core changes:
  - Add support of octal mode I/O transfer
  - Add a bunch of SPI NOR entries to the flash_info table

  SPI NOR controller driver changes:
  - cadence-quadspi:
    * Add support for Octal SPI controller
    * write upto 8-bytes data in STIG mode
  - mtk-quadspi:
    * rename config to a common one
    * add SNOR_HWCAPS_READ to spi_nor_hwcaps mask

MAINTAINERS:
- Add Tudor as SPI-NOR co-maintainer
parents b0dd77a7 225c0eda
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+1 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ Required properties:
- compatible : should be one of the following:
	Generic default - "cdns,qspi-nor".
	For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
	For TI AM654 SoC  - "ti,am654-ospi", "cdns,qspi-nor".
- reg : Contains two entries, each of which is a tuple consisting of a
	physical address and length. The first entry is the address and
	length of the controller register set. The second entry is the
+2 −1
Original line number Diff line number Diff line
* Serial NOR flash controller for MTK MT81xx (and similar)
* Serial NOR flash controller for MediaTek SoCs

Required properties:
- compatible: 	  For mt8173, compatible should be "mediatek,mt8173-nor",
@@ -10,6 +10,7 @@ Required properties:
		  "mediatek,mt2712-nor", "mediatek,mt8173-nor"
		  "mediatek,mt7622-nor", "mediatek,mt8173-nor"
		  "mediatek,mt7623-nor", "mediatek,mt8173-nor"
		  "mediatek,mt7629-nor", "mediatek,mt8173-nor"
		  "mediatek,mt8173-nor"
- reg: 		  physical base address and length of the controller's register
- clocks: 	  the phandle of the clocks needed by the nor controller
+1 −0
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@@ -14303,6 +14303,7 @@ F: arch/arm/mach-spear/

SPI NOR SUBSYSTEM
M:	Marek Vasut <marek.vasut@gmail.com>
M:	Tudor Ambarus <tudor.ambarus@microchip.com>
L:	linux-mtd@lists.infradead.org
W:	http://www.linux-mtd.infradead.org/
Q:	http://patchwork.ozlabs.org/project/linux-mtd/list/
+8 −1
Original line number Diff line number Diff line
@@ -195,7 +195,14 @@ static int m25p_probe(struct spi_mem *spimem)
	spi_mem_set_drvdata(spimem, flash);
	flash->spimem = spimem;

	if (spi->mode & SPI_RX_QUAD) {
	if (spi->mode & SPI_RX_OCTAL) {
		hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;

		if (spi->mode & SPI_TX_OCTAL)
			hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
					SNOR_HWCAPS_PP_1_1_8 |
					SNOR_HWCAPS_PP_1_8_8);
	} else if (spi->mode & SPI_RX_QUAD) {
		hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;

		if (spi->mode & SPI_TX_QUAD)
+8 −8
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@@ -7,14 +7,6 @@ menuconfig MTD_SPI_NOR

if MTD_SPI_NOR

config MTD_MT81xx_NOR
	tristate "Mediatek MT81xx SPI NOR flash controller"
	depends on HAS_IOMEM
	help
	  This enables access to SPI NOR flash, using MT81xx SPI NOR flash
	  controller. This controller does not support generic SPI BUS, it only
	  supports SPI NOR Flash.

config MTD_SPI_NOR_USE_4K_SECTORS
	bool "Use small 4096 B erase sectors"
	default y
@@ -66,6 +58,14 @@ config SPI_HISI_SFC
	help
	  This enables support for hisilicon SPI-NOR flash controller.

config SPI_MTK_QUADSPI
	tristate "MediaTek Quad SPI controller"
	depends on HAS_IOMEM
	help
	  This enables support for the Quad SPI controller in master mode.
	  This controller does not support generic SPI. It only supports
	  SPI NOR.

config SPI_NXP_SPIFI
	tristate "NXP SPI Flash Interface (SPIFI)"
	depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
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