clk: add pre and post change rate callbacks

There are scenarios where a rate change could result in a configuration
change for both the targeted clock and its parent.

For example, setting the rate for a clock could require both slewing its parent
PLL as well as adjusting the clock's divider values. Due to the fact that
rate change propagation always occurs from parent to child, we could exceed
the allowed operating frequencies for the clock as the parent slews to a higher
frequency before increasing the downstream divider.

Add a pre change call back which allows the clock to adjust its divider
appropriately before any rate change has occurred from its parents to ensure
that the clock's requirements are always within safe frequencies during parent
rate changes. The symmetrical post change call back handles the scenario where
the divider adjusts to a lower value and can only be safely adjusted after the
parent rate changes.

Change-Id: I4f8cf9df6fc256d065599de86a34cf99eae4d853
Signed-off-by: David Dai <daidavid1@codeaurora.org>