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Commit 88dfc9a3 authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: separate amdgpu_rlc into a single file 



Separate the function and struct of RLC from the file of GFX.
Abstract the function of amdgpu_gfx_rlc_fini.

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fdb81fd7

drivers/gpu/drm/amd/amdgpu/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -105,6 +105,7 @@ amdgpu-y += \ 
# add GFX block

amdgpu-y += \

	amdgpu_gfx.o \

	amdgpu_rlc.o \

	gfx_v8_0.o \

	gfx_v9_0.o

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#include <drm/drmP.h>

#include "amdgpu.h"

#include "amdgpu_gfx.h"

#include "amdgpu_rlc.h"



/* delay 0.1 second to enable gfx off feature */

#define GFX_OFF_DELAY_ENABLE         msecs_to_jiffies(100)

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

+1 −59
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 
 */

#include "clearstate_defs.h"

#include "amdgpu_ring.h"

#include "amdgpu_rlc.h"



/* GFX current status */

#define AMDGPU_GFX_NORMAL_MODE			0x00000000L
@@ -37,65 +38,6 @@ 
#define AMDGPU_GFX_CG_DISABLED_MODE		0x00000004L

#define AMDGPU_GFX_LBPW_DISABLED_MODE		0x00000008L





struct amdgpu_rlc_funcs {

	void (*enter_safe_mode)(struct amdgpu_device *adev);

	void (*exit_safe_mode)(struct amdgpu_device *adev);

	int  (*init)(struct amdgpu_device *adev);

	void (*fini)(struct amdgpu_device *adev);

	int  (*resume)(struct amdgpu_device *adev);

	void (*stop)(struct amdgpu_device *adev);

	void (*reset)(struct amdgpu_device *adev);

	void (*start)(struct amdgpu_device *adev);

};



struct amdgpu_rlc {

	/* for power gating */

	struct amdgpu_bo	*save_restore_obj;

	uint64_t		save_restore_gpu_addr;

	volatile uint32_t	*sr_ptr;

	const u32               *reg_list;

	u32                     reg_list_size;

	/* for clear state */

	struct amdgpu_bo	*clear_state_obj;

	uint64_t		clear_state_gpu_addr;

	volatile uint32_t	*cs_ptr;

	const struct cs_section_def   *cs_data;

	u32                     clear_state_size;

	/* for cp tables */

	struct amdgpu_bo	*cp_table_obj;

	uint64_t		cp_table_gpu_addr;

	volatile uint32_t	*cp_table_ptr;

	u32                     cp_table_size;



	/* safe mode for updating CG/PG state */

	bool in_safe_mode;

	const struct amdgpu_rlc_funcs *funcs;



	/* for firmware data */

	u32 save_and_restore_offset;

	u32 clear_state_descriptor_offset;

	u32 avail_scratch_ram_locations;

	u32 reg_restore_list_size;

	u32 reg_list_format_start;

	u32 reg_list_format_separate_start;

	u32 starting_offsets_start;

	u32 reg_list_format_size_bytes;

	u32 reg_list_size_bytes;

	u32 reg_list_format_direct_reg_list_length;

	u32 save_restore_list_cntl_size_bytes;

	u32 save_restore_list_gpm_size_bytes;

	u32 save_restore_list_srm_size_bytes;



	u32 *register_list_format;

	u32 *register_restore;

	u8 *save_restore_list_cntl;

	u8 *save_restore_list_gpm;

	u8 *save_restore_list_srm;



	bool is_rlc_v2_1;

};



#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES



struct amdgpu_mec {

drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c

0 → 100644
+57 −0
Original line number Diff line number Diff line 


/*

 * Copyright 2014 Advanced Micro Devices, Inc.

 * Copyright 2008 Red Hat Inc.

 * Copyright 2009 Jerome Glisse.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#include "amdgpu.h"

#include "amdgpu_gfx.h"

#include "amdgpu_rlc.h"



/**

 * amdgpu_gfx_rlc_fini - Free BO which used for RLC

 *

 * @adev: amdgpu_device pointer

 *

 * Free three BO which is used for rlc_save_restore_block, rlc_clear_state_block

 * and rlc_jump_table_block.

 */

void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev)

{

	/* save restore block */

	if (adev->gfx.rlc.save_restore_obj) {

		amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj,

				      &adev->gfx.rlc.save_restore_gpu_addr,

				      (void **)&adev->gfx.rlc.sr_ptr);

	}



	/* clear state block */

	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,

			      &adev->gfx.rlc.clear_state_gpu_addr,

			      (void **)&adev->gfx.rlc.cs_ptr);



	/* jump table block */

	amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,

			      &adev->gfx.rlc.cp_table_gpu_addr,

			      (void **)&adev->gfx.rlc.cp_table_ptr);

}

drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h

0 → 100644
+89 −0
Original line number Diff line number Diff line 


/*

 * Copyright 2014 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef __AMDGPU_RLC_H__

#define __AMDGPU_RLC_H__



#include "clearstate_defs.h"



struct amdgpu_rlc_funcs {

	void (*enter_safe_mode)(struct amdgpu_device *adev);

	void (*exit_safe_mode)(struct amdgpu_device *adev);

	int  (*init)(struct amdgpu_device *adev);

	int  (*resume)(struct amdgpu_device *adev);

	void (*stop)(struct amdgpu_device *adev);

	void (*reset)(struct amdgpu_device *adev);

	void (*start)(struct amdgpu_device *adev);

};



struct amdgpu_rlc {

	/* for power gating */

	struct amdgpu_bo	*save_restore_obj;

	uint64_t		save_restore_gpu_addr;

	volatile uint32_t	*sr_ptr;

	const u32               *reg_list;

	u32                     reg_list_size;

	/* for clear state */

	struct amdgpu_bo	*clear_state_obj;

	uint64_t		clear_state_gpu_addr;

	volatile uint32_t	*cs_ptr;

	const struct cs_section_def   *cs_data;

	u32                     clear_state_size;

	/* for cp tables */

	struct amdgpu_bo	*cp_table_obj;

	uint64_t		cp_table_gpu_addr;

	volatile uint32_t	*cp_table_ptr;

	u32                     cp_table_size;



	/* safe mode for updating CG/PG state */

	bool in_safe_mode;

	const struct amdgpu_rlc_funcs *funcs;



	/* for firmware data */

	u32 save_and_restore_offset;

	u32 clear_state_descriptor_offset;

	u32 avail_scratch_ram_locations;

	u32 reg_restore_list_size;

	u32 reg_list_format_start;

	u32 reg_list_format_separate_start;

	u32 starting_offsets_start;

	u32 reg_list_format_size_bytes;

	u32 reg_list_size_bytes;

	u32 reg_list_format_direct_reg_list_length;

	u32 save_restore_list_cntl_size_bytes;

	u32 save_restore_list_gpm_size_bytes;

	u32 save_restore_list_srm_size_bytes;



	u32 *register_list_format;

	u32 *register_restore;

	u8 *save_restore_list_cntl;

	u8 *save_restore_list_gpm;

	u8 *save_restore_list_srm;



	bool is_rlc_v2_1;

};



void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev);



#endif