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Commit 8890fe5f authored by Huang Rui's avatar Huang Rui Committed by Alex Deucher
Browse files

drm/amd/powerplay: introduce smu power source type to handle AC/DC source for each asic 



This patch introduces new smu power source type, it's to handle the different
AC/DC source defines for each asic with the same smu ip.

Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarKevin Wang <kevin1.wang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 97384904

drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

+10 −0
Original line number Diff line number Diff line
@@ -243,6 +243,13 @@ enum smu_clk_type 
	SMU_CLK_COUNT,

};



enum smu_power_src_type

{

	SMU_POWER_SOURCE_AC,

	SMU_POWER_SOURCE_DC,

	SMU_POWER_SOURCE_COUNT,

};



enum smu_feature_mask

{

	SMU_FEATURE_DPM_PREFETCHER_BIT,
@@ -513,6 +520,7 @@ struct pptable_funcs { 
	int (*get_smu_clk_index)(struct smu_context *smu, uint32_t index);

	int (*get_smu_feature_index)(struct smu_context *smu, uint32_t index);

	int (*get_smu_table_index)(struct smu_context *smu, uint32_t index);

	int (*get_smu_power_index)(struct smu_context *smu, uint32_t index);

	int (*run_afll_btc)(struct smu_context *smu);

	int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);

	enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
@@ -819,6 +827,8 @@ struct smu_funcs 
	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_feature_index? (smu)->ppt_funcs->get_smu_feature_index((smu), (msg)) : -EINVAL) : -EINVAL)

#define smu_table_get_index(smu, tab) \

	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_table_index? (smu)->ppt_funcs->get_smu_table_index((smu), (tab)) : -EINVAL) : -EINVAL)

#define smu_power_get_index(smu, src) \

	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_power_index? (smu)->ppt_funcs->get_smu_power_index((smu), (src)) : -EINVAL) : -EINVAL)

#define smu_run_afll_btc(smu) \

	((smu)->ppt_funcs? ((smu)->ppt_funcs->run_afll_btc? (smu)->ppt_funcs->run_afll_btc((smu)) : 0) : 0)

#define smu_get_allowed_feature_mask(smu, feature_mask, num) \

drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h

+3 −0
Original line number Diff line number Diff line
@@ -51,6 +51,9 @@ 
#define TAB_MAP(tab) \

	[SMU_TABLE_##tab] = TABLE_##tab



#define PWR_MAP(tab) \

	[SMU_POWER_SOURCE_##tab] = POWER_SOURCE_##tab



struct smu_11_0_max_sustainable_clocks {

	uint32_t display_clock;

	uint32_t phy_clock;

drivers/gpu/drm/amd/powerplay/navi10_ppt.c

+19 −0
Original line number Diff line number Diff line
@@ -171,6 +171,11 @@ static int navi10_table_map[SMU_TABLE_COUNT] = { 
	TAB_MAP(PACE),

};



static int navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {

	PWR_MAP(AC),

	PWR_MAP(DC),

};



static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)

{

	int val;
@@ -223,6 +228,19 @@ static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index) 
	return val;

}



static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)

{

	int val;

	if (index >= SMU_POWER_SOURCE_COUNT)

		return -EINVAL;



	val = navi10_pwr_src_map[index];

	if (val >= POWER_SOURCE_COUNT)

		return -EINVAL;



	return val;

}



#define FEATURE_MASK(feature) (1UL << feature)

static int

navi10_get_allowed_feature_mask(struct smu_context *smu,
@@ -459,6 +477,7 @@ static const struct pptable_funcs navi10_ppt_funcs = { 
	.get_smu_clk_index = navi10_get_smu_clk_index,

	.get_smu_feature_index = navi10_get_smu_feature_index,

	.get_smu_table_index = navi10_get_smu_table_index,

	.get_smu_power_index = navi10_get_pwr_src_index,

	.get_allowed_feature_mask = navi10_get_allowed_feature_mask,

	.set_default_dpm_table = navi10_set_default_dpm_table,

};

drivers/gpu/drm/amd/powerplay/smu_v11_0.c

+1 −1
Original line number Diff line number Diff line
@@ -1038,7 +1038,7 @@ static int smu_v11_0_get_power_limit(struct smu_context *smu, 
		mutex_unlock(&smu->mutex);

	} else {

		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,

						  POWER_SOURCE_AC << 16);

			smu_power_get_index(smu, SMU_POWER_SOURCE_AC) << 16);

		if (ret) {

			pr_err("[%s] get PPT limit failed!", __func__);

			return ret;

drivers/gpu/drm/amd/powerplay/vega20_ppt.c

+19 −0
Original line number Diff line number Diff line
@@ -202,6 +202,11 @@ static int vega20_table_map[SMU_TABLE_COUNT] = { 
	TAB_MAP(OVERDRIVE),

};



static int vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {

	PWR_MAP(AC),

	PWR_MAP(DC),

};



static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index)

{

	int val;
@@ -215,6 +220,19 @@ static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index) 
	return val;

}



static int vega20_get_pwr_src_index(struct smu_context *smc, uint32_t index)

{

	int val;

	if (index >= SMU_POWER_SOURCE_COUNT)

		return -EINVAL;



	val = vega20_pwr_src_map[index];

	if (val >= POWER_SOURCE_COUNT)

		return -EINVAL;



	return val;

}



static int vega20_get_smu_feature_index(struct smu_context *smc, uint32_t index)

{

	int val;
@@ -3105,6 +3123,7 @@ static const struct pptable_funcs vega20_ppt_funcs = { 
	.get_smu_clk_index = vega20_get_smu_clk_index,

	.get_smu_feature_index = vega20_get_smu_feature_index,

	.get_smu_table_index = vega20_get_smu_table_index,

	.get_smu_power_index = vega20_get_pwr_src_index,

	.run_afll_btc = vega20_run_btc_afll,

	.get_allowed_feature_mask = vega20_get_allowed_feature_mask,

	.get_current_power_state = vega20_get_current_power_state,