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Commit 97384904 authored by Huang Rui's avatar Huang Rui Committed by Alex Deucher
Browse files

drm/amd/powerplay: move Watermarks_t uses into asic level 



This patch moves the rest of Watermarks_t uses into asic level. It's to avoid
the conflicts with different asic.

Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarKevin Wang <kevin1.wang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8b1f4c87

drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

+4 −0
Original line number Diff line number Diff line
@@ -575,6 +575,8 @@ struct pptable_funcs { 
	int (*get_current_activity_percent)(struct smu_context *smu,

					    enum amd_pp_sensors sensor,

					    uint32_t *value);

	int (*set_watermarks_table)(struct smu_context *smu, void *watermarks,

				    struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);

};



struct smu_funcs
@@ -863,6 +865,8 @@ struct smu_funcs 
	((smu)->ppt_funcs->set_ppfeature_status ? (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)

#define smu_get_ppfeature_status(smu, buf) \

	((smu)->ppt_funcs->get_ppfeature_status ? (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)

#define smu_set_watermarks_table(smu, tab, clock_ranges) \

	((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)



extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,

				   uint16_t *size, uint8_t *frev, uint8_t *crev,

drivers/gpu/drm/amd/powerplay/smu_v11_0.c

+2 −61
Original line number Diff line number Diff line
@@ -1401,65 +1401,6 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu, 
	return ret;

}



static int smu_v11_0_set_watermarks_table(struct smu_context *smu,

					  Watermarks_t *table, struct

					  dm_pp_wm_sets_with_clock_ranges_soc15

					  *clock_ranges)

{

	int i;



	if (!table || !clock_ranges)

		return -EINVAL;



	if (clock_ranges->num_wm_dmif_sets > 4 ||

	    clock_ranges->num_wm_mcif_sets > 4)

                return -EINVAL;



        for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {

		table->WatermarkRow[1][i].MinClock =

			cpu_to_le16((uint16_t)

			(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /

			1000));

		table->WatermarkRow[1][i].MaxClock =

			cpu_to_le16((uint16_t)

			(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /

			1000));

		table->WatermarkRow[1][i].MinUclk =

			cpu_to_le16((uint16_t)

			(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /

			1000));

		table->WatermarkRow[1][i].MaxUclk =

			cpu_to_le16((uint16_t)

			(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /

			1000));

		table->WatermarkRow[1][i].WmSetting = (uint8_t)

				clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;

        }



	for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {

		table->WatermarkRow[0][i].MinClock =

			cpu_to_le16((uint16_t)

			(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /

			1000));

		table->WatermarkRow[0][i].MaxClock =

			cpu_to_le16((uint16_t)

			(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /

			1000));

		table->WatermarkRow[0][i].MinUclk =

			cpu_to_le16((uint16_t)

			(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /

			1000));

		table->WatermarkRow[0][i].MaxUclk =

			cpu_to_le16((uint16_t)

			(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /

			1000));

		table->WatermarkRow[0][i].WmSetting = (uint8_t)

				clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;

        }



	return 0;

}



static int

smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct

					  dm_pp_wm_sets_with_clock_ranges_soc15
@@ -1467,12 +1408,12 @@ smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct 
{

	int ret = 0;

	struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];

	Watermarks_t *table = watermarks->cpu_addr;

	void *table = watermarks->cpu_addr;



	if (!smu->disable_watermark &&

	    smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&

	    smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {

		smu_v11_0_set_watermarks_table(smu, table, clock_ranges);

		smu_set_watermarks_table(smu, table, clock_ranges);

		smu->watermarks_bitmap |= WATERMARKS_EXIST;

		smu->watermarks_bitmap &= ~WATERMARKS_LOADED;

	}

drivers/gpu/drm/amd/powerplay/vega20_ppt.c

+61 −0
Original line number Diff line number Diff line
@@ -3035,6 +3035,66 @@ static int vega20_get_current_activity_percent(struct smu_context *smu, 
	return 0;

}



static int vega20_set_watermarks_table(struct smu_context *smu,

				       void *watermarks, struct

				       dm_pp_wm_sets_with_clock_ranges_soc15

				       *clock_ranges)

{

	int i;

	Watermarks_t *table = watermarks;



	if (!table || !clock_ranges)

		return -EINVAL;



	if (clock_ranges->num_wm_dmif_sets > 4 ||

	    clock_ranges->num_wm_mcif_sets > 4)

		return -EINVAL;



	for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {

		table->WatermarkRow[1][i].MinClock =

			cpu_to_le16((uint16_t)

			(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /

			1000));

		table->WatermarkRow[1][i].MaxClock =

			cpu_to_le16((uint16_t)

			(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /

			1000));

		table->WatermarkRow[1][i].MinUclk =

			cpu_to_le16((uint16_t)

			(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /

			1000));

		table->WatermarkRow[1][i].MaxUclk =

			cpu_to_le16((uint16_t)

			(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /

			1000));

		table->WatermarkRow[1][i].WmSetting = (uint8_t)

				clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;

	}



	for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {

		table->WatermarkRow[0][i].MinClock =

			cpu_to_le16((uint16_t)

			(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /

			1000));

		table->WatermarkRow[0][i].MaxClock =

			cpu_to_le16((uint16_t)

			(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /

			1000));

		table->WatermarkRow[0][i].MinUclk =

			cpu_to_le16((uint16_t)

			(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /

			1000));

		table->WatermarkRow[0][i].MaxUclk =

			cpu_to_le16((uint16_t)

			(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /

			1000));

		table->WatermarkRow[0][i].WmSetting = (uint8_t)

				clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;

	}



	return 0;

}



static const struct pptable_funcs vega20_ppt_funcs = {

	.tables_init = vega20_tables_init,

	.alloc_dpm_context = vega20_allocate_dpm_context,
@@ -3082,6 +3142,7 @@ static const struct pptable_funcs vega20_ppt_funcs = { 
	.get_fan_speed_percent = vega20_get_fan_speed_percent,

	.get_gpu_power = vega20_get_gpu_power,

	.get_current_activity_percent = vega20_get_current_activity_percent,

	.set_watermarks_table = vega20_set_watermarks_table,

};



void vega20_set_ppt_funcs(struct smu_context *smu)