Loading drivers/clk/qcom/common.c +20 −0 Original line number Diff line number Diff line Loading @@ -11,12 +11,14 @@ #include <linux/clk-provider.h> #include <linux/reset-controller.h> #include <linux/of.h> #include <linux/clk/qcom.h> #include "common.h" #include "clk-rcg.h" #include "clk-regmap.h" #include "reset.h" #include "gdsc.h" #include "vdd-level.h" struct qcom_cc { struct qcom_reset_controller reset; Loading Loading @@ -371,4 +373,22 @@ void qcom_cc_sync_state(struct device *dev, const struct qcom_cc_desc *desc) } EXPORT_SYMBOL(qcom_cc_sync_state); int qcom_clk_get_voltage(struct clk *clk, unsigned long rate) { struct clk_regmap *rclk; struct clk_hw *hw = __clk_get_hw(clk); int vdd_level; if (!clk_is_regmap_clk(hw)) return -EINVAL; rclk = to_clk_regmap(hw); vdd_level = clk_find_vdd_level(hw, &rclk->vdd_data, rate); if (vdd_level < 0) return vdd_level; return rclk->vdd_data.vdd_class->vdd_uv[vdd_level]; } EXPORT_SYMBOL(qcom_clk_get_voltage); MODULE_LICENSE("GPL v2"); drivers/clk/qcom/vdd-class.c +3 −0 Original line number Diff line number Diff line Loading @@ -149,6 +149,9 @@ int clk_find_vdd_level(struct clk_hw *hw, { int level; if (!vdd_data->num_rate_max) return -ENODATA; /* * For certain PLLs, due to the limitation in the bits allocated for * programming the fractional divider, the actual rate of the PLL will Loading include/linux/clk/qcom.h 0 → 100644 +13 −0 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2020 The Linux Foundation. All rights reserved. */ #ifndef __LINUX_CLK_QCOM_H_ #define __LINUX_CLK_QCOM_H_ #include <linux/clk-provider.h> int qcom_clk_get_voltage(struct clk *clk, unsigned long rate); #endif /* __LINUX_CLK_QCOM_H_ */ Loading
drivers/clk/qcom/common.c +20 −0 Original line number Diff line number Diff line Loading @@ -11,12 +11,14 @@ #include <linux/clk-provider.h> #include <linux/reset-controller.h> #include <linux/of.h> #include <linux/clk/qcom.h> #include "common.h" #include "clk-rcg.h" #include "clk-regmap.h" #include "reset.h" #include "gdsc.h" #include "vdd-level.h" struct qcom_cc { struct qcom_reset_controller reset; Loading Loading @@ -371,4 +373,22 @@ void qcom_cc_sync_state(struct device *dev, const struct qcom_cc_desc *desc) } EXPORT_SYMBOL(qcom_cc_sync_state); int qcom_clk_get_voltage(struct clk *clk, unsigned long rate) { struct clk_regmap *rclk; struct clk_hw *hw = __clk_get_hw(clk); int vdd_level; if (!clk_is_regmap_clk(hw)) return -EINVAL; rclk = to_clk_regmap(hw); vdd_level = clk_find_vdd_level(hw, &rclk->vdd_data, rate); if (vdd_level < 0) return vdd_level; return rclk->vdd_data.vdd_class->vdd_uv[vdd_level]; } EXPORT_SYMBOL(qcom_clk_get_voltage); MODULE_LICENSE("GPL v2");
drivers/clk/qcom/vdd-class.c +3 −0 Original line number Diff line number Diff line Loading @@ -149,6 +149,9 @@ int clk_find_vdd_level(struct clk_hw *hw, { int level; if (!vdd_data->num_rate_max) return -ENODATA; /* * For certain PLLs, due to the limitation in the bits allocated for * programming the fractional divider, the actual rate of the PLL will Loading
include/linux/clk/qcom.h 0 → 100644 +13 −0 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2020 The Linux Foundation. All rights reserved. */ #ifndef __LINUX_CLK_QCOM_H_ #define __LINUX_CLK_QCOM_H_ #include <linux/clk-provider.h> int qcom_clk_get_voltage(struct clk *clk, unsigned long rate); #endif /* __LINUX_CLK_QCOM_H_ */