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Commit 0f30cf7e authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "drivers: irqchip: mpm: Add QTI SoC interrupt controller"

parents b1d9b568 67371f6d
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+1 −0
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@@ -115,3 +115,4 @@ CONFIG_DEVFREQ_GOV_QCOM_ADRENO_TZ=m
CONFIG_USB_ROLE_SWITCH=m
# CONFIG_QCOM_MINIDUMP is not set
CONFIG_QCOM_EUD=m
CONFIG_MSM_RPM_SMD=m
+1 −0
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@@ -124,3 +124,4 @@ CONFIG_QCOM_MINIDUMP=y
CONFIG_ARM_QCOM_DEVFREQ_QOSLAT=y
CONFIG_IPC_LOGGING=y
# CONFIG_FTRACE_STARTUP_TEST is not set
CONFIG_MSM_RPM_SMD=y
+1 −0
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@@ -100,3 +100,4 @@ CONFIG_CRC8=y
CONFIG_MSM_REMOTEQDSS=y
CONFIG_LKDTM=y
CONFIG_MSM_GCC_HOLI=y
CONFIG_MSM_RPM_SMD=y
+11 −0
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@@ -493,6 +493,17 @@ config TI_SCI_INTA_IRQCHIP
	  If you wish to use interrupt aggregator irq resources managed by the
	  TI System Controller, say Y here. Otherwise, say N.

config QCOM_MPM
	bool "QCOM MPM"
	depends on ARCH_QCOM
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	help
	  MSM Power Manager driver to manage and configure wakeup
	  IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
	  Say yes here to enable the MSM Power Manager interrupt
	  controller to use as a wakeup interrupt controller.

config SIFIVE_PLIC
	bool "SiFive Platform-Level Interrupt Controller"
	depends on RISCV
+1 −0
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@@ -98,6 +98,7 @@ obj-$(CONFIG_NDS32) += irq-ativic32.o
obj-$(CONFIG_QCOM_PDC)			+= qcom-pdc.o
obj-$(CONFIG_CSKY_MPINTC)		+= irq-csky-mpintc.o
obj-$(CONFIG_CSKY_APB_INTC)		+= irq-csky-apb-intc.o
obj-$(CONFIG_QCOM_MPM)			+= qcom-mpm.o
obj-$(CONFIG_SIFIVE_PLIC)		+= irq-sifive-plic.o
obj-$(CONFIG_IMX_IRQSTEER)		+= irq-imx-irqsteer.o
obj-$(CONFIG_MADERA_IRQ)		+= irq-madera.o
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