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Commit 80432c73 authored by Andi Kleen's avatar Andi Kleen
Browse files

perf vendor events intel: Add uncore events for Sandy Bridge client 

Add V15 of Sandy Bridge uncore events

Cc: jolsa@kernel.org
Link: http://lkml.kernel.org/n/tip-2qkwutpwljdue8jmwk3xqdbl@git.kernel.org


Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
parent 9c4e2e25

tools/perf/pmu-events/arch/x86/sandybridge/uncore.json

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+314 −0
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[

  {

    "Unit": "CBO",

    "EventCode": "0x22",

    "UMask": "0x01",

    "EventName": "UNC_CBO_XSNP_RESPONSE.MISS",

    "BriefDescription": "A snoop misses in some processor core.",

    "PublicDescription": "A snoop misses in some processor core.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x22",

    "UMask": "0x02",

    "EventName": "UNC_CBO_XSNP_RESPONSE.INVAL",

    "BriefDescription": "A snoop invalidates a non-modified line in some processor core.",

    "PublicDescription": "A snoop invalidates a non-modified line in some processor core.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x22",

    "UMask": "0x04",

    "EventName": "UNC_CBO_XSNP_RESPONSE.HIT",

    "BriefDescription": "A snoop hits a non-modified line in some processor core.",

    "PublicDescription": "A snoop hits a non-modified line in some processor core.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x22",

    "UMask": "0x08",

    "EventName": "UNC_CBO_XSNP_RESPONSE.HITM",

    "BriefDescription": "A snoop hits a modified line in some processor core.",

    "PublicDescription": "A snoop hits a modified line in some processor core.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x22",

    "UMask": "0x10",

    "EventName": "UNC_CBO_XSNP_RESPONSE.INVAL_M",

    "BriefDescription": "A snoop invalidates a modified line in some processor core.",

    "PublicDescription": "A snoop invalidates a modified line in some processor core.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x22",

    "UMask": "0x20",

    "EventName": "UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER",

    "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.",

    "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x22",

    "UMask": "0x40",

    "EventName": "UNC_CBO_XSNP_RESPONSE.XCORE_FILTER",

    "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.",

    "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x22",

    "UMask": "0x80",

    "EventName": "UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER",

    "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",

    "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x01",

    "EventName": "UNC_CBO_CACHE_LOOKUP.M",

    "BriefDescription": "LLC lookup request that access cache and found line in M-state.",

    "PublicDescription": "LLC lookup request that access cache and found line in M-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x02",

    "EventName": "UNC_CBO_CACHE_LOOKUP.E",

    "BriefDescription": "LLC lookup request that access cache and found line in E-state.",

    "PublicDescription": "LLC lookup request that access cache and found line in E-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x04",

    "EventName": "UNC_CBO_CACHE_LOOKUP.S",

    "BriefDescription": "LLC lookup request that access cache and found line in S-state.",

    "PublicDescription": "LLC lookup request that access cache and found line in S-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x08",

    "EventName": "UNC_CBO_CACHE_LOOKUP.I",

    "BriefDescription": "LLC lookup request that access cache and found line in I-state.",

    "PublicDescription": "LLC lookup request that access cache and found line in I-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x10",

    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_FILTER",

    "BriefDescription": "Filter on processor core initiated cacheable read requests.",

    "PublicDescription": "Filter on processor core initiated cacheable read requests.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x20",

    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_FILTER",

    "BriefDescription": "Filter on processor core initiated cacheable write requests.",

    "PublicDescription": "Filter on processor core initiated cacheable write requests.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x40",

    "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER",

    "BriefDescription": "Filter on external snoop requests.",

    "PublicDescription": "Filter on external snoop requests.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x80",

    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER",

    "BriefDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.",

    "PublicDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "ARB",

    "EventCode": "0x80",

    "UMask": "0x01",

    "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",

    "BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",

    "PublicDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",

    "Counter": "0",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "ARB",

    "EventCode": "0x81",

    "UMask": "0x01",

    "EventName": "UNC_ARB_TRK_REQUESTS.ALL",

    "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",

    "PublicDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "ARB",

    "EventCode": "0x81",

    "UMask": "0x20",

    "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",

    "BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",

    "PublicDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "ARB",

    "EventCode": "0x81",

    "UMask": "0x80",

    "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS",

    "BriefDescription": "Counts the number of LLC evictions allocated.",

    "PublicDescription": "Counts the number of LLC evictions allocated.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "ARB",

    "EventCode": "0x83",

    "UMask": "0x01",

    "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL",

    "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",

    "PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",

    "Counter": "0",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "ARB",

    "EventCode": "0x84",

    "UMask": "0x01",

    "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",

    "BriefDescription": "Number of requests allocated in Coherency Tracker.",

    "PublicDescription": "Number of requests allocated in Coherency Tracker.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "ARB",

    "EventCode": "0x80",

    "UMask": "0x01",

    "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",

    "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",

    "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",

    "Counter": "0,1",

    "CounterMask": "1",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "ARB",

    "EventCode": "0x80",

    "UMask": "0x01",

    "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL",

    "BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",

    "PublicDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",

    "Counter": "0,1",

    "CounterMask": "10",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "ARB",

    "EventCode": "0x0",

    "UMask": "0x01",

    "EventName": "UNC_CLOCK.SOCKET",

    "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",

    "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",

    "Counter": "Fixed",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x06",

    "EventName": "UNC_CBO_CACHE_LOOKUP.ES",

    "BriefDescription": "LLC lookup request that access cache and found line in E-state or S-state.",

    "PublicDescription": "LLC lookup request that access cache and found line in E-state or S-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  }

]
 
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