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Commit 7f6d2188 authored by James Morse's avatar James Morse Committed by Greg Kroah-Hartman
Browse files

arm64: errata: Remove AES hwcap for COMPAT tasks 



commit 44b3834b2eed595af07021b1c64e6f9bc396398b upstream.

Cortex-A57 and Cortex-A72 have an erratum where an interrupt that
occurs between a pair of AES instructions in aarch32 mode may corrupt
the ELR. The task will subsequently produce the wrong AES result.

The AES instructions are part of the cryptographic extensions, which are
optional. User-space software will detect the support for these
instructions from the hwcaps. If the platform doesn't support these
instructions a software implementation should be used.

Remove the hwcap bits on affected parts to indicate user-space should
not use the AES instructions.

Acked-by: default avatarArd Biesheuvel <ardb@kernel.org>
Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20220714161523.279570-3-james.morse@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
[florian: resolved conflicts in arch/arm64/tools/cpucaps and cpu_errata.c]
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent aae35081

Documentation/arm64/silicon-errata.rst

+4 −0
Original line number Diff line number Diff line
@@ -70,8 +70,12 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A57      | #834220         | ARM64_ERRATUM_834220        |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A57      | #1742098        | ARM64_ERRATUM_1742098       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A72      | #853709         | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A72      | #1655431        | ARM64_ERRATUM_1742098       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |

arch/arm64/Kconfig

+16 −0
Original line number Diff line number Diff line
@@ -574,6 +574,22 @@ config ARM64_ERRATUM_1542419 


	  If unsure, say Y.



config ARM64_ERRATUM_1742098

	bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"

	depends on COMPAT

	default y

	help

	  This option removes the AES hwcap for aarch32 user-space to

	  workaround erratum 1742098 on Cortex-A57 and Cortex-A72.



	  Affected parts may corrupt the AES state if an interrupt is

	  taken between a pair of AES instructions. These instructions

	  are only present if the cryptography extensions are present.

	  All software should have a fallback implementation for CPUs

	  that don't implement the cryptography extensions.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -56,7 +56,8 @@ 
#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM	46

#define ARM64_WORKAROUND_1542419		47

#define ARM64_SPECTRE_BHB			48

#define ARM64_WORKAROUND_1742098		49



#define ARM64_NCAPS				49

#define ARM64_NCAPS				50



#endif /* __ASM_CPUCAPS_H */

arch/arm64/kernel/cpu_errata.c

+16 −0
Original line number Diff line number Diff line
@@ -817,6 +817,14 @@ static const struct arm64_cpu_capabilities erratum_843419_list[] = { 
};

#endif



#ifdef CONFIG_ARM64_ERRATUM_1742098

static struct midr_range broken_aarch32_aes[] = {

	MIDR_RANGE(MIDR_CORTEX_A57, 0, 1, 0xf, 0xf),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),

	{},

};

#endif



const struct arm64_cpu_capabilities arm64_errata[] = {

#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE

	{
@@ -997,6 +1005,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.matches = has_neoverse_n1_erratum_1542419,

		.cpu_enable = cpu_enable_trap_ctr_access,

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_1742098

	{

		.desc = "ARM erratum 1742098",

		.capability = ARM64_WORKAROUND_1742098,

		CAP_MIDR_RANGE_LIST(broken_aarch32_aes),

		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,

	},

#endif

	{

	}

arch/arm64/kernel/cpufeature.c

+12 −1
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#include <asm/cpufeature.h>

#include <asm/cpu_ops.h>

#include <asm/fpsimd.h>

#include <asm/hwcap.h>

#include <asm/mmu_context.h>

#include <asm/processor.h>

#include <asm/sysreg.h>
@@ -1280,6 +1281,14 @@ static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 
}

#endif



static void elf_hwcap_fixup(void)

{

#ifdef CONFIG_ARM64_ERRATUM_1742098

	if (cpus_have_const_cap(ARM64_WORKAROUND_1742098))

		compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES;

#endif /* ARM64_ERRATUM_1742098 */

}



static const struct arm64_cpu_capabilities arm64_features[] = {

	{

		.desc = "GIC system register CPU interface",
@@ -2103,8 +2112,10 @@ void __init setup_cpu_features(void) 
	mark_const_caps_ready();

	setup_elf_hwcaps(arm64_elf_hwcaps);



	if (system_supports_32bit_el0())

	if (system_supports_32bit_el0()) {

		setup_elf_hwcaps(compat_elf_hwcaps);

		elf_hwcap_fixup();

	}



	if (system_uses_ttbr0_pan())

		pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");