Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7e2a1b51 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Add a6xx GMU performance counters 



Add three new groups to the a6xx performance counters for a620, a650,
and a660 to expose the GMU_XOCLK, GMU_GMUCLK and GMU_PERF counters.

Change-Id: Ic0dedbad07805bee4b6977e683e1161e4d500c1c
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent ba7d8b88

drivers/gpu/msm/a6xx_reg.h

+30 −0
Original line number Diff line number Diff line
@@ -983,6 +983,36 @@ 
#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H	0x1F84D

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L	0x1F84E

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H	0x1F84F

#define A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_0_L 0x1F850

#define A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_0_H 0x1F851

#define A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_1_L 0x1F852

#define A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_1_H 0x1F853

#define A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_2	0x1F860

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_6_L	0x1F870

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_6_H	0x1F871

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_7_L	0x1F872

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_7_H	0x1F843

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_8_L	0x1F874

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_8_H	0x1F875

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_9_L	0x1F876

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_9_H	0x1F877

#define A6XX_GMU_CX_GMU_ALWAYS_ON_COUNTER_L	0x1F888

#define A6XX_GMU_CX_GMU_ALWAYS_ON_COUNTER_H	0x1F889

#define A6XX_GMU_CX_GMU_PERF_COUNTER_ENABLE	0x1F8A0

#define A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_0	0x1F8A1

#define A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_1	0x1F8A2

#define A6XX_GMU_CX_GMU_PERF_COUNTER_0_L	0x1F8A4

#define A6XX_GMU_CX_GMU_PERF_COUNTER_0_H	0x1F8A5

#define A6XX_GMU_CX_GMU_PERF_COUNTER_1_L	0x1F8A6

#define A6XX_GMU_CX_GMU_PERF_COUNTER_1_H	0x1F8A7

#define A6XX_GMU_CX_GMU_PERF_COUNTER_2_L	0x1F8A8

#define A6XX_GMU_CX_GMU_PERF_COUNTER_2_H	0x1F8A9

#define A6XX_GMU_CX_GMU_PERF_COUNTER_3_L	0x1F8AA

#define A6XX_GMU_CX_GMU_PERF_COUNTER_3_H	0x1F8AB

#define A6XX_GMU_CX_GMU_PERF_COUNTER_4_L	0x1F8AC

#define A6XX_GMU_CX_GMU_PERF_COUNTER_4_H	0x1F8AD

#define A6XX_GMU_CX_GMU_PERF_COUNTER_5_L	0x1F8AE

#define A6XX_GMU_CX_GMU_PERF_COUNTER_5_H	0x1F8AF

#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL	0x1F8C0

#define A6XX_GMU_PWR_COL_INTER_FRAME_HYST	0x1F8C1

#define A6XX_GMU_PWR_COL_SPTPRAC_HYST		0x1F8C2

drivers/gpu/msm/adreno-gpulist.h

+22 −11
Original line number Diff line number Diff line
@@ -894,7 +894,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = { 
			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -922,7 +922,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = { 
			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -950,7 +950,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a619 = { 
			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -977,7 +977,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a619_variant = { 
		.compatible = "qcom,adreno-gpu-a619-holi",

		.features =  ADRENO_PREEMPTION | ADRENO_CONTENT_PROTECTION,

		.gpudev = &adreno_a619_holi_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -1092,7 +1092,12 @@ static const struct a6xx_protected_regs a620_protected_regs[] = { 
	{ A6XX_CP_PROTECT_REG + 30, 0x0be20, 0x0d5ff, 1 },

	{ A6XX_CP_PROTECT_REG + 31, 0x0f000, 0x0fbff, 1 },

	{ A6XX_CP_PROTECT_REG + 32, 0x0fc00, 0x11bff, 0 },

	{ A6XX_CP_PROTECT_REG + 47, 0x11c00, 0x11c00, 1 },

	{ A6XX_CP_PROTECT_REG + 33, 0x18400, 0x1a3ff, 1 },

	{ A6XX_CP_PROTECT_REG + 34, 0x1a800, 0x1c7ff, 1 },

	{ A6XX_CP_PROTECT_REG + 35, 0x1f400, 0x1f843, 1 },

	{ A6XX_CP_PROTECT_REG + 36, 0x1f844, 0x1f8bf, 0 },

	{ A6XX_CP_PROTECT_REG + 37, 0x1f887, 0x1f8a2, 1 },

	{ A6XX_CP_PROTECT_REG + 47, 0x1f8c0, 0x1f8c0, 1 },

	{ 0 },

};
@@ -1195,7 +1200,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = { 
			ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT |

			ADRENO_IFPC | ADRENO_PREEMPTION,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M, //Verified 1MB

		.bus_width = 32,
@@ -1333,7 +1338,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = { 
		DEFINE_ADRENO_REV(ADRENO_REV_A680, 6, 8, 0, ANY_ID),

		.features = ADRENO_RPMH | ADRENO_GPMU,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_2M,

		.bus_width = 32,
@@ -1411,7 +1416,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = { 
			ADRENO_IOCOHERENT | ADRENO_PREEMPTION | ADRENO_GPMU |

			ADRENO_IFPC,

		.gpudev = &adreno_a6xx_rgmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_4K),

		.bus_width = 32,
@@ -1437,7 +1442,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = { 
			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -1464,7 +1469,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a610 = { 
		.features = ADRENO_CONTENT_PROTECTION |

			ADRENO_PREEMPTION,

		.gpudev = &adreno_a6xx_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_4K),

		.bus_width = 32,
@@ -1569,7 +1574,13 @@ static const struct a6xx_protected_regs a660_protected_regs[] = { 
	{ A6XX_CP_PROTECT_REG + 31, 0x0d000, 0x0d5ff, 1 },

	{ A6XX_CP_PROTECT_REG + 32, 0x0f000, 0x0fbff, 1 },

	{ A6XX_CP_PROTECT_REG + 33, 0x0fc00, 0x11bff, 0 },

	{ A6XX_CP_PROTECT_REG + 47, 0x11c00, 0x11c00, 1 },

	{ A6XX_CP_PROTECT_REG + 34, 0x18400, 0x1a3ff, 1 },

	{ A6XX_CP_PROTECT_REG + 35, 0x1a400, 0x1c3ff, 1 },

	{ A6XX_CP_PROTECT_REG + 36, 0x1f400, 0x1f843, 1 },

	{ A6XX_CP_PROTECT_REG + 37, 0x1f844, 0x1f8bf, 0 },

	{ A6XX_CP_PROTECT_REG + 38, 0x1f860, 0x1f860, 1 },

	{ A6XX_CP_PROTECT_REG + 39, 0x1f887, 0x1f8a2, 1 },

	{ A6XX_CP_PROTECT_REG + 47, 0x1f8c0, 0x1f8c0, 1 },

	{ 0 },

};

drivers/gpu/msm/adreno_a6xx.h

+1 −0
Original line number Diff line number Diff line
@@ -407,4 +407,5 @@ int a6xx_perfcounter_update(struct adreno_device *adreno_dev, 


extern const struct adreno_perfcounters adreno_a630_perfcounters;

extern const struct adreno_perfcounters adreno_a6xx_perfcounters;

extern const struct adreno_perfcounters adreno_a6xx_legacy_perfcounters;

#endif

drivers/gpu/msm/adreno_a6xx_perfcounter.c

+219 −0
Original line number Diff line number Diff line
@@ -269,6 +269,99 @@ static u64 a6xx_counter_alwayson_read(struct adreno_device *adreno_dev, 
	return a6xx_read_alwayson(adreno_dev) + reg->value;

}



static void a6xx_write_gmu_counter_enable(struct kgsl_device *device,

		struct adreno_perfcount_register *reg, u32 bit, u32 countable)

{

	u32 val;



	kgsl_regread(device, reg->select, &val);

	val &= ~(0xff << bit);

	val |= countable << bit;

	kgsl_regwrite(device, reg->select, val);



}



static int a6xx_counter_gmu_xoclk_enable(struct adreno_device *adreno_dev,

		const struct adreno_perfcount_group *group,

		unsigned int counter, unsigned int countable)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct adreno_perfcount_register *reg = &group->regs[counter];



	if (countable > 0xff)

		return -EINVAL;



	if (counter >= 6 && !adreno_is_a660(adreno_dev))

		return -EINVAL;



	/*

	 * Counters [0:3] are in select 1 bit offsets 0, 8, 16 and 24

	 * Counters [4:5] are in select 2 bit offset 0, 8

	 * Counters [6:9] are in select 3 bit offset 0, 8, 16 and 24

	 */



	if (counter == 4 || counter == 5)

		counter -= 4;

	else if (counter >= 6)

		counter -= 6;



	a6xx_write_gmu_counter_enable(device, reg, counter * 8, countable);



	reg->value = 0;



	kgsl_regwrite(device, A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);



	return 0;

}



static int a6xx_counter_gmu_gmuclk_enable(struct adreno_device *adreno_dev,

		const struct adreno_perfcount_group *group,

		unsigned int counter, unsigned int countable)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct adreno_perfcount_register *reg = &group->regs[counter];



	if (countable > 0xff)

		return -EINVAL;



	/*

	 * The two counters are stuck into GMU_CX_GMU_POWER_COUNTER_SELECT_1

	 * at bit offset 16 and 24

	 */

	a6xx_write_gmu_counter_enable(device, reg,

		16 + (counter * 8), countable);



	kgsl_regwrite(device, A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);



	reg->value = 0;

	return 0;

}



static int a6xx_counter_gmu_perf_enable(struct adreno_device *adreno_dev,

		const struct adreno_perfcount_group *group,

		unsigned int counter, unsigned int countable)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct adreno_perfcount_register *reg = &group->regs[counter];



	if (countable > 0xff)

		return -EINVAL;



	/*

	 * Counters [0:3] are in select 1 bit offsets 0, 8, 16 and 24

	 * Counters [4:5] are in select 2 bit offset 0, 8

	 */



	if (counter >= 4)

		counter -= 4;



	a6xx_write_gmu_counter_enable(device, reg, counter * 8, countable);



	kgsl_regwrite(device, A6XX_GMU_CX_GMU_PERF_COUNTER_ENABLE, 1);



	reg->value = 0;

	return 0;

}



static struct adreno_perfcount_register a6xx_perfcounters_cp[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CP_0_LO,
@@ -611,6 +704,73 @@ static struct adreno_perfcount_register a6xx_perfcounters_gbif_pwr[] = { 
		A6XX_GBIF_PWR_CNT_HIGH2, -1, A6XX_GBIF_PERF_PWR_CNT_EN },

};



#define GMU_COUNTER(lo, hi, sel) \

	{ .countable = KGSL_PERFCOUNTER_NOT_USED, \

	  .offset = lo, .offset_hi = hi, .select = sel }



static struct adreno_perfcount_register a6xx_perfcounters_gmu_xoclk[] = {

	GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H,

		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0),

	GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H,

		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0),

	GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H,

		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0),

	GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H,

		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0),

	GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H,

		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1),

	GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H,

		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1),

	GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_6_L,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_6_H,

		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_2),

	GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_7_L,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_7_H,

		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_2),

	GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_8_L,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_8_H,

		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_2),

	GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_9_L,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_9_H,

		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_2),

};



static struct adreno_perfcount_register a6xx_perfcounters_gmu_gmuclk[] = {

	GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_0_L,

		A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_0_H,

		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1),

	GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_1_L,

		A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_1_H,

		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1),

};



static struct adreno_perfcount_register a6xx_perfcounters_gmu_perf[] = {

	GMU_COUNTER(A6XX_GMU_CX_GMU_PERF_COUNTER_0_L,

		A6XX_GMU_CX_GMU_PERF_COUNTER_0_H,

		A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_0),

	GMU_COUNTER(A6XX_GMU_CX_GMU_PERF_COUNTER_1_L,

		A6XX_GMU_CX_GMU_PERF_COUNTER_1_H,

		A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_0),

	GMU_COUNTER(A6XX_GMU_CX_GMU_PERF_COUNTER_2_L,

		A6XX_GMU_CX_GMU_PERF_COUNTER_2_H,

		A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_0),

	GMU_COUNTER(A6XX_GMU_CX_GMU_PERF_COUNTER_3_L,

		A6XX_GMU_CX_GMU_PERF_COUNTER_3_H,

		A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_0),

	GMU_COUNTER(A6XX_GMU_CX_GMU_PERF_COUNTER_4_L,

		A6XX_GMU_CX_GMU_PERF_COUNTER_4_H,

		A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_1),

	GMU_COUNTER(A6XX_GMU_CX_GMU_PERF_COUNTER_5_L,

		A6XX_GMU_CX_GMU_PERF_COUNTER_5_H,

		A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_1),

};



static struct adreno_perfcount_register a6xx_perfcounters_alwayson[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_CP_ALWAYS_ON_COUNTER_LO,

		A6XX_CP_ALWAYS_ON_COUNTER_HI, -1 },
@@ -674,6 +834,50 @@ static const struct adreno_perfcount_group a630_perfcounter_groups 
		a6xx_counter_alwayson_enable, a6xx_counter_alwayson_read),

};



static const struct adreno_perfcount_group

a6xx_legacy_perfcounter_groups [KGSL_PERFCOUNTER_GROUP_MAX] = {

	A6XX_PERFCOUNTER_GROUP(CP, cp,

		a6xx_counter_enable, a6xx_counter_read),

	A6XX_PERFCOUNTER_GROUP_FLAGS(RBBM, rbbm, 0,

		a6xx_counter_enable, a6xx_counter_read),

	A6XX_PERFCOUNTER_GROUP(PC, pc,

		a6xx_counter_enable, a6xx_counter_read),

	A6XX_PERFCOUNTER_GROUP(VFD, vfd,

		a6xx_counter_enable, a6xx_counter_read),

	A6XX_PERFCOUNTER_GROUP(HLSQ, hlsq,

		a6xx_counter_inline_enable, a6xx_counter_read),

	A6XX_PERFCOUNTER_GROUP(VPC, vpc,

		a6xx_counter_enable, a6xx_counter_read),

	A6XX_PERFCOUNTER_GROUP(CCU, ccu,

		a6xx_counter_enable, a6xx_counter_read),

	A6XX_PERFCOUNTER_GROUP(CMP, cmp,

		a6xx_counter_enable, a6xx_counter_read),

	A6XX_PERFCOUNTER_GROUP(TSE, tse,

		a6xx_counter_enable, a6xx_counter_read),

	A6XX_PERFCOUNTER_GROUP(RAS, ras,

		a6xx_counter_enable, a6xx_counter_read),

	A6XX_PERFCOUNTER_GROUP(LRZ, lrz,

		a6xx_counter_enable, a6xx_counter_read),

	A6XX_PERFCOUNTER_GROUP(UCHE, uche,

		a6xx_counter_enable, a6xx_counter_read),

	A6XX_PERFCOUNTER_GROUP(TP, tp,

		a6xx_counter_inline_enable, a6xx_counter_read),

	A6XX_PERFCOUNTER_GROUP(SP, sp,

		a6xx_counter_inline_enable, a6xx_counter_read),

	A6XX_PERFCOUNTER_GROUP(RB, rb,

		a6xx_counter_enable, a6xx_counter_read),

	A6XX_PERFCOUNTER_GROUP(VSC, vsc,

		a6xx_counter_enable, a6xx_counter_read),

	A6XX_PERFCOUNTER_GROUP_FLAGS(VBIF, gbif, 0,

		a6xx_counter_gbif_enable, a6xx_counter_read_norestore),

	A6XX_PERFCOUNTER_GROUP_FLAGS(VBIF_PWR, gbif_pwr,

		ADRENO_PERFCOUNTER_GROUP_FIXED,

		a6xx_counter_gbif_pwr_enable, a6xx_counter_read_norestore),

	A6XX_PERFCOUNTER_GROUP_FLAGS(ALWAYSON, alwayson,

		ADRENO_PERFCOUNTER_GROUP_FIXED,

		a6xx_counter_alwayson_enable, a6xx_counter_alwayson_read),

};



static const struct adreno_perfcount_group a6xx_perfcounter_groups

				[KGSL_PERFCOUNTER_GROUP_MAX] = {

	A6XX_PERFCOUNTER_GROUP(CP, cp,
@@ -716,6 +920,21 @@ static const struct adreno_perfcount_group a6xx_perfcounter_groups 
	A6XX_PERFCOUNTER_GROUP_FLAGS(ALWAYSON, alwayson,

		ADRENO_PERFCOUNTER_GROUP_FIXED,

		a6xx_counter_alwayson_enable, a6xx_counter_alwayson_read),

	A6XX_PERFCOUNTER_GROUP_FLAGS(GMU_XOCLK, gmu_xoclk, 0,

		a6xx_counter_gmu_xoclk_enable, a6xx_counter_read_norestore),

	A6XX_PERFCOUNTER_GROUP_FLAGS(GMU_GMUCLK, gmu_gmuclk, 0,

		a6xx_counter_gmu_gmuclk_enable, a6xx_counter_read_norestore),

	A6XX_PERFCOUNTER_GROUP_FLAGS(GMU_PERF, gmu_perf, 0,

		a6xx_counter_gmu_perf_enable, a6xx_counter_read_norestore),

};



/* a610, a612, a616, a618 and a619 do not have the GMU registers.

 * a605, a608, a615, a630, a640 and a680 don't have enough room in the

 * CP_PROTECT registers so the GMU counters are not accessible

 */

const struct adreno_perfcounters adreno_a6xx_legacy_perfcounters = {

	a6xx_legacy_perfcounter_groups,

	ARRAY_SIZE(a6xx_legacy_perfcounter_groups),

};



const struct adreno_perfcounters adreno_a630_perfcounters = {

include/uapi/linux/msm_kgsl.h

+8 −1
Original line number Diff line number Diff line
@@ -464,7 +464,14 @@ struct kgsl_context_property_fault { 
#define KGSL_PERFCOUNTER_GROUP_CP_PWR 0x21

#define KGSL_PERFCOUNTER_GROUP_GPMU_PWR 0x22

#define KGSL_PERFCOUNTER_GROUP_ALWAYSON_PWR 0x23

#define KGSL_PERFCOUNTER_GROUP_MAX 0x24

#define KGSL_PERFCOUNTER_GROUP_GLC 0x24

#define KGSL_PERFCOUNTER_GROUP_FCHE 0x25

#define KGSL_PERFCOUNTER_GROUP_MHUB 0x26

#define KGSL_PERFCOUNTER_GROUP_GMU_XOCLK 0x27

#define KGSL_PERFCOUNTER_GROUP_GMU_GMUCLK  0x28

#define KGSL_PERFCOUNTER_GROUP_GMU_PERF  0x29

#define KGSL_PERFCOUNTER_GROUP_SW 0x2a

#define KGSL_PERFCOUNTER_GROUP_MAX 0x2b



#define KGSL_PERFCOUNTER_NOT_USED 0xFFFFFFFF

#define KGSL_PERFCOUNTER_BROKEN 0xFFFFFFFE