Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ba7d8b88 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Finish up the last bits of the perfcounter transition 



Now that all the perfcounter code is safely target specific finish up the
transition. First move the perfcounter definition from the gpudev to the
adreno_gpu_core so that we can specify the list per target which gives us
more control than modifying the gpudev at runtime or creating multiple
gpudev structs just for the perfcounter deltas.

Further drive home the point by marking the perfcounter and groups
as const. The perfcounter migration has now completed. You don't have
to go home, but you can't stay here.

Change-Id: Ic0dedbad4b4dbb8e9e49ed94dc23b97fc578324b
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 100ff4e1

drivers/gpu/msm/adreno-gpulist.h

+27 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306 = { 
		DEFINE_ADRENO_REV(ADRENO_REV_A306, 3, 0, 6, 0),

		.features = ADRENO_SOFT_FAULT_DETECT,

		.gpudev = &adreno_a3xx_gpudev,

		.perfcounters = &adreno_a3xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_128K,

		.bus_width = 0,
@@ -48,6 +49,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306a = { 
		DEFINE_ADRENO_REV(ADRENO_REV_A306A, 3, 0, 6, 0x20),

		.features = ADRENO_SOFT_FAULT_DETECT,

		.gpudev = &adreno_a3xx_gpudev,

		.perfcounters = &adreno_a3xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_128K,

		.bus_width = 16,
@@ -68,6 +70,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a304 = { 
		DEFINE_ADRENO_REV(ADRENO_REV_A304, 3, 0, 4, 0),

		.features = ADRENO_SOFT_FAULT_DETECT,

		.gpudev = &adreno_a3xx_gpudev,

		.perfcounters = &adreno_a3xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = (SZ_64K + SZ_32K),

		.bus_width = 0,
@@ -192,6 +195,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v2 = { 
			ADRENO_PREEMPTION |

			ADRENO_CONTENT_PROTECTION,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.bus_width = 32,
@@ -218,6 +222,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = { 
			ADRENO_PREEMPTION |

			ADRENO_CONTENT_PROTECTION,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.bus_width = 32,
@@ -284,6 +289,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a505 = { 
		DEFINE_ADRENO_REV(ADRENO_REV_A505, 5, 0, 5, ANY_ID),

		.features = ADRENO_PREEMPTION,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.bus_width = 16,
@@ -303,6 +309,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a506 = { 
		.features = ADRENO_PREEMPTION |

			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.bus_width = 16,
@@ -381,6 +388,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a510 = { 
	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A510, 5, 1, 0, ANY_ID),

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_256K,

		.bus_width = 16,
@@ -506,6 +514,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a540v2 = { 
			ADRENO_CONTENT_PROTECTION |

			ADRENO_GPMU | ADRENO_SPTP_PC,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.bus_width = 32,
@@ -589,6 +598,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a512 = { 
		.features = ADRENO_PREEMPTION |

			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_256K + SZ_16K),

		.bus_width = 32,
@@ -608,6 +618,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a508 = { 
		.features = ADRENO_PREEMPTION |

			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.bus_width = 32,
@@ -783,6 +794,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = { 
			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION |

			ADRENO_IOCOHERENT | ADRENO_PREEMPTION,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a630_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.bus_width = 32,
@@ -882,6 +894,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = { 
			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -909,6 +922,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = { 
			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -936,6 +950,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a619 = { 
			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -962,6 +977,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a619_variant = { 
		.compatible = "qcom,adreno-gpu-a619-holi",

		.features =  ADRENO_PREEMPTION | ADRENO_CONTENT_PROTECTION,

		.gpudev = &adreno_a619_holi_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -1088,6 +1104,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = { 
			ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD |

			ADRENO_APRIV,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -1178,6 +1195,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = { 
			ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT |

			ADRENO_IFPC | ADRENO_PREEMPTION,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M, //Verified 1MB

		.bus_width = 32,
@@ -1258,6 +1276,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = { 
			ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |

			ADRENO_IFPC | ADRENO_APRIV,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */

		.bus_width = 32,
@@ -1287,6 +1306,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = { 
			ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD |

			ADRENO_LM | ADRENO_APRIV,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */

		.bus_width = 32,
@@ -1313,6 +1333,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = { 
		DEFINE_ADRENO_REV(ADRENO_REV_A680, 6, 8, 0, ANY_ID),

		.features = ADRENO_RPMH | ADRENO_GPMU,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_2M,

		.bus_width = 32,
@@ -1390,6 +1411,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = { 
			ADRENO_IOCOHERENT | ADRENO_PREEMPTION | ADRENO_GPMU |

			ADRENO_IFPC,

		.gpudev = &adreno_a6xx_rgmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_4K),

		.bus_width = 32,
@@ -1415,6 +1437,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = { 
			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -1441,6 +1464,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a610 = { 
		.features = ADRENO_CONTENT_PROTECTION |

			ADRENO_PREEMPTION,

		.gpudev = &adreno_a6xx_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_4K),

		.bus_width = 32,
@@ -1556,6 +1580,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660 = { 
				ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |

				ADRENO_IFPC | ADRENO_PREEMPTION,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_512K,

		.bus_width = 32,
@@ -1587,6 +1612,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660v2 = { 
				ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |

				ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_512K,

		.bus_width = 32,
@@ -1619,6 +1645,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660_shima = { 
				ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |

				ADRENO_IFPC,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_512K,

		.bus_width = 32,

drivers/gpu/msm/adreno.h

+1 −2
Original line number Diff line number Diff line
@@ -392,6 +392,7 @@ struct adreno_gpu_core { 
	const char *compatible;

	unsigned long features;

	struct adreno_gpudev *gpudev;

	const struct adreno_perfcounters *perfcounters;

	unsigned long gmem_base;

	size_t gmem_size;

	u32 bus_width;
@@ -762,8 +763,6 @@ struct adreno_gpudev { 
	const struct adreno_ft_perf_counters *ft_perf_counters;

	unsigned int ft_perf_counters_count;



	struct adreno_perfcounters *perfcounters;



	struct adreno_coresight *coresight[2];



	unsigned int vbif_xin_halt_ctrl0_mask;

drivers/gpu/msm/adreno_a3xx.c

+0 −1
Original line number Diff line number Diff line
@@ -1236,7 +1236,6 @@ struct adreno_gpudev adreno_a3xx_gpudev = { 
	.reg_offsets = a3xx_register_offsets,

	.ft_perf_counters = a3xx_ft_perf_counters,

	.ft_perf_counters_count = ARRAY_SIZE(a3xx_ft_perf_counters),

	.perfcounters = &adreno_a3xx_perfcounters,

	.irq_handler = a3xx_irq_handler,

	.vbif_xin_halt_ctrl0_mask = A30X_VBIF_XIN_HALT_CTRL0_MASK,

	.probe = a3xx_probe,

drivers/gpu/msm/adreno_a3xx.h

+1 −1
Original line number Diff line number Diff line
@@ -44,6 +44,6 @@ unsigned int a3xx_irq_pending(struct adreno_device *adreno_dev); 
void a3xx_snapshot(struct adreno_device *adreno_dev,

		struct kgsl_snapshot *snapshot);



extern struct adreno_perfcounters adreno_a3xx_perfcounters;

extern const struct adreno_perfcounters adreno_a3xx_perfcounters;



#endif /*__A3XX_H */

drivers/gpu/msm/adreno_a3xx_perfcounter.c

+11 −10
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ 
#define VBIF2_PERF_PWR_CLR_REG_EN_OFF 8



static int a3xx_counter_enable(struct adreno_device *adreno_dev,

		struct adreno_perfcount_group *group,

		const struct adreno_perfcount_group *group,

		unsigned int counter, unsigned int countable)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@@ -32,7 +32,7 @@ static int a3xx_counter_enable(struct adreno_device *adreno_dev, 
}



static u64 a3xx_counter_read(struct adreno_device *adreno_dev,

		struct adreno_perfcount_group *group,

		const struct adreno_perfcount_group *group,

		unsigned int counter)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@@ -52,14 +52,14 @@ static u64 a3xx_counter_read(struct adreno_device *adreno_dev, 
}



static int a3xx_counter_pwr_enable(struct adreno_device *adreno_dev,

		struct adreno_perfcount_group *group,

		const struct adreno_perfcount_group *group,

		unsigned int counter, unsigned int countable)

{

	return 0;

}



static u64 a3xx_counter_pwr_read(struct adreno_device *adreno_dev,

		struct adreno_perfcount_group *group,

		const struct adreno_perfcount_group *group,

		unsigned int counter)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@@ -83,7 +83,7 @@ static u64 a3xx_counter_pwr_read(struct adreno_device *adreno_dev, 
}



static int a3xx_counter_vbif_enable(struct adreno_device *adreno_dev,

		struct adreno_perfcount_group *group,

		const struct adreno_perfcount_group *group,

		unsigned int counter, unsigned int countable)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@@ -113,7 +113,7 @@ static int a3xx_counter_vbif_enable(struct adreno_device *adreno_dev, 
}



static u64 a3xx_counter_vbif_read(struct adreno_device *adreno_dev,

		struct adreno_perfcount_group *group,

		const struct adreno_perfcount_group *group,

		unsigned int counter)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@@ -133,7 +133,7 @@ static u64 a3xx_counter_vbif_read(struct adreno_device *adreno_dev, 
}



static int a3xx_counter_vbif_pwr_enable(struct adreno_device *adreno_dev,

		struct adreno_perfcount_group *group,

		const struct adreno_perfcount_group *group,

		unsigned int counter, unsigned int countable)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@@ -154,7 +154,7 @@ static int a3xx_counter_vbif_pwr_enable(struct adreno_device *adreno_dev, 
}



static u64 a3xx_counter_vbif_pwr_read(struct adreno_device *adreno_dev,

		struct adreno_perfcount_group *group,

		const struct adreno_perfcount_group *group,

		unsigned int counter)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@@ -356,7 +356,8 @@ static struct adreno_perfcount_register a3xx_perfcounters_vbif2_pwr[] = { 
#define A3XX_PERFCOUNTER_GROUP_FLAGS(offset, name, flags, enable, read) \

	ADRENO_PERFCOUNTER_GROUP_FLAGS(a3xx, offset, name, flags, enable, read)



static struct adreno_perfcount_group a3xx_perfcounter_groups[] = {

static const struct adreno_perfcount_group

a3xx_perfcounter_groups[KGSL_PERFCOUNTER_GROUP_MAX] = {

	A3XX_PERFCOUNTER_GROUP(CP, cp,

		a3xx_counter_enable, a3xx_counter_read),

	A3XX_PERFCOUNTER_GROUP(RBBM, rbbm,
@@ -392,7 +393,7 @@ static struct adreno_perfcount_group a3xx_perfcounter_groups[] = { 


};



struct adreno_perfcounters adreno_a3xx_perfcounters = {

const struct adreno_perfcounters adreno_a3xx_perfcounters = {

	a3xx_perfcounter_groups,

	ARRAY_SIZE(a3xx_perfcounter_groups),

};