msm: mhi: Handle PCIe events from the common work queue

A couple of instances are observed in which MHI got D3hot and D0 in
a very short span, but the device processed D0 first and D3hot later.
This is resulting s/w state machine going out of sync with h/w
resulting MHI driver to trigger syserr.

Below is the sequence of events:

1) received: EP_PCIE_PM_D3_HOT_EVENT
2) IPA DMA successfully disabled
3) received: EP_PCIE_PM_D0_EVENT
4) Start handling EP_PCIE_PM_D0_EVENT, Current states M-3, D0
   Nothing to do, already in D0 state
5) Start handling EP_PCIE_PM_D3_HOT_EVENT, Current state M-3, D0
6) Start handling MHI_DEV_EVENT_M0_STATE, Current state M-3 & D3_HOT
   MHI_DEV_EVENT_M0_STATE: illegal in current MHI states: M-3 & D3_HOT

Though both works (from the same work queue) are waiting on the same
mutex lock, somehow the work which is processing D0 got the lock first.
The only possibility is priority inversion.

To avoid this scenario use mhi_sm_wq for PCIe event which ensures one
execution at any given time.

commit <37ea867103f2>("msm: ep-pcie: Use threaded irq for PERST
de-assertion handling"), ensures PERST de-assertion events are handled
at max possible priority. So we don't really need high priority system
work queue for handling other PCIe events.

Change-Id: Id147bf8eae7b09999289c70be87dd98b9f68ba3b
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>