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Commit 7a34a96e authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Enable CPU cooling device for lahaina"

parents 675f81ae 1aaeb67b

qcom/lahaina.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ 
			dynamic-power-coefficient = <100>;

			cpu-idle-states = <&SLVR_RAIL_OFF>;

			next-level-cache = <&L2_0>;

			#cooling-cells = <2>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -98,6 +99,7 @@ 
			dynamic-power-coefficient = <100>;

			cpu-idle-states = <&SLVR_RAIL_OFF>;

			next-level-cache = <&L2_1>;

			#cooling-cells = <2>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -118,6 +120,7 @@ 
			dynamic-power-coefficient = <100>;

			cpu-idle-states = <&SLVR_RAIL_OFF>;

			next-level-cache = <&L2_2>;

			#cooling-cells = <2>;

			L2_2: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -138,6 +141,7 @@ 
			dynamic-power-coefficient = <100>;

			cpu-idle-states = <&SLVR_RAIL_OFF>;

			next-level-cache = <&L2_3>;

			#cooling-cells = <2>;

			L2_3: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -158,6 +162,7 @@ 
			dynamic-power-coefficient = <515>;

			cpu-idle-states = <&GOLD_RAIL_OFF>;

			next-level-cache = <&L2_4>;

			#cooling-cells = <2>;

			L2_4: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x40000>;
@@ -178,6 +183,7 @@ 
			dynamic-power-coefficient = <515>;

			cpu-idle-states = <&GOLD_RAIL_OFF>;

			next-level-cache = <&L2_5>;

			#cooling-cells = <2>;

			L2_5: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x40000>;
@@ -198,6 +204,7 @@ 
			dynamic-power-coefficient = <515>;

			cpu-idle-states = <&GOLD_RAIL_OFF>;

			next-level-cache = <&L2_6>;

			#cooling-cells = <2>;

			L2_6: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x40000>;
@@ -218,6 +225,7 @@ 
			dynamic-power-coefficient = <845>;

			cpu-idle-states = <&GOLD_RAIL_OFF>;

			next-level-cache = <&L2_7>;

			#cooling-cells = <2>;

			L2_7: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x40000>;