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Commit 1aaeb67b authored by Ram Chandrasekar's avatar Ram Chandrasekar
Browse files

ARM: dts: msm: Enable CPU cooling device for lahaina 

Enable CPU cooling device to mitigate the CPU frequency in lahaina.
Adding the #cooling-cells property will enable the cpufreq driver to
register CPU cooling device.

Change-Id: I50e2fcdcc259337d2f4501a75b1a756546cbbbd0
parent f8215580

qcom/lahaina.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -71,6 +71,7 @@ 
			dynamic-power-coefficient = <100>;

			cpu-idle-states = <&SLVR_RAIL_OFF>;

			next-level-cache = <&L2_0>;

			#cooling-cells = <2>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -97,6 +98,7 @@ 
			dynamic-power-coefficient = <100>;

			cpu-idle-states = <&SLVR_RAIL_OFF>;

			next-level-cache = <&L2_1>;

			#cooling-cells = <2>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -117,6 +119,7 @@ 
			dynamic-power-coefficient = <100>;

			cpu-idle-states = <&SLVR_RAIL_OFF>;

			next-level-cache = <&L2_2>;

			#cooling-cells = <2>;

			L2_2: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -137,6 +140,7 @@ 
			dynamic-power-coefficient = <100>;

			cpu-idle-states = <&SLVR_RAIL_OFF>;

			next-level-cache = <&L2_3>;

			#cooling-cells = <2>;

			L2_3: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -157,6 +161,7 @@ 
			dynamic-power-coefficient = <515>;

			cpu-idle-states = <&GOLD_RAIL_OFF>;

			next-level-cache = <&L2_4>;

			#cooling-cells = <2>;

			L2_4: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x40000>;
@@ -177,6 +182,7 @@ 
			dynamic-power-coefficient = <515>;

			cpu-idle-states = <&GOLD_RAIL_OFF>;

			next-level-cache = <&L2_5>;

			#cooling-cells = <2>;

			L2_5: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x40000>;
@@ -197,6 +203,7 @@ 
			dynamic-power-coefficient = <515>;

			cpu-idle-states = <&GOLD_RAIL_OFF>;

			next-level-cache = <&L2_6>;

			#cooling-cells = <2>;

			L2_6: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x40000>;
@@ -217,6 +224,7 @@ 
			dynamic-power-coefficient = <845>;

			cpu-idle-states = <&GOLD_RAIL_OFF>;

			next-level-cache = <&L2_7>;

			#cooling-cells = <2>;

			L2_7: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x40000>;