Loading msm/sde/sde_crtc.c +7 −1 Original line number Diff line number Diff line Loading @@ -1668,6 +1668,11 @@ static void _sde_crtc_blend_setup(struct drm_crtc *crtc, return; } if (test_bit(SDE_CRTC_DIRTY_DIM_LAYERS, &sde_crtc->revalidate_mask)) { set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, sde_crtc_state->dirty); clear_bit(SDE_CRTC_DIRTY_DIM_LAYERS, &sde_crtc->revalidate_mask); } for (i = 0; i < sde_crtc->num_mixers; i++) { if (!mixer[i].hw_lm) { SDE_ERROR("invalid lm or ctl assigned to mixer\n"); Loading Loading @@ -3977,6 +3982,7 @@ void sde_crtc_reset_sw_state(struct drm_crtc *crtc) { struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state); struct drm_plane *plane; struct sde_crtc *sde_crtc = to_sde_crtc(crtc); /* mark planes, mixers, and other blocks dirty for next update */ drm_atomic_crtc_for_each_plane(plane, crtc) Loading @@ -3986,7 +3992,7 @@ void sde_crtc_reset_sw_state(struct drm_crtc *crtc) sde_crtc_clear_cached_mixer_cfg(crtc); /* mark other properties which need to be dirty for next update */ set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty); set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, &sde_crtc->revalidate_mask); if (cstate->num_ds_enabled) set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty); } Loading msm/sde/sde_crtc.h +2 −0 Original line number Diff line number Diff line Loading @@ -254,6 +254,7 @@ struct sde_crtc_misr_info { * @feature_list : list of color processing features supported on a crtc * @active_list : list of color processing features are active * @dirty_list : list of color processing features are dirty * @revalidate_mask : stores dirty flags to revalidate after idlepc * @ad_dirty : list containing ad properties that are dirty * @ad_active : list containing ad properties that are active * @crtc_lock : crtc lock around create, destroy and access. Loading Loading @@ -348,6 +349,7 @@ struct sde_crtc { spinlock_t spin_lock; spinlock_t fevent_spin_lock; bool kickoff_in_progress; unsigned long revalidate_mask; /* for handling internal event thread */ struct sde_crtc_event event_cache[SDE_CRTC_MAX_EVENT_COUNT]; Loading Loading
msm/sde/sde_crtc.c +7 −1 Original line number Diff line number Diff line Loading @@ -1668,6 +1668,11 @@ static void _sde_crtc_blend_setup(struct drm_crtc *crtc, return; } if (test_bit(SDE_CRTC_DIRTY_DIM_LAYERS, &sde_crtc->revalidate_mask)) { set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, sde_crtc_state->dirty); clear_bit(SDE_CRTC_DIRTY_DIM_LAYERS, &sde_crtc->revalidate_mask); } for (i = 0; i < sde_crtc->num_mixers; i++) { if (!mixer[i].hw_lm) { SDE_ERROR("invalid lm or ctl assigned to mixer\n"); Loading Loading @@ -3977,6 +3982,7 @@ void sde_crtc_reset_sw_state(struct drm_crtc *crtc) { struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state); struct drm_plane *plane; struct sde_crtc *sde_crtc = to_sde_crtc(crtc); /* mark planes, mixers, and other blocks dirty for next update */ drm_atomic_crtc_for_each_plane(plane, crtc) Loading @@ -3986,7 +3992,7 @@ void sde_crtc_reset_sw_state(struct drm_crtc *crtc) sde_crtc_clear_cached_mixer_cfg(crtc); /* mark other properties which need to be dirty for next update */ set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty); set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, &sde_crtc->revalidate_mask); if (cstate->num_ds_enabled) set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty); } Loading
msm/sde/sde_crtc.h +2 −0 Original line number Diff line number Diff line Loading @@ -254,6 +254,7 @@ struct sde_crtc_misr_info { * @feature_list : list of color processing features supported on a crtc * @active_list : list of color processing features are active * @dirty_list : list of color processing features are dirty * @revalidate_mask : stores dirty flags to revalidate after idlepc * @ad_dirty : list containing ad properties that are dirty * @ad_active : list containing ad properties that are active * @crtc_lock : crtc lock around create, destroy and access. Loading Loading @@ -348,6 +349,7 @@ struct sde_crtc { spinlock_t spin_lock; spinlock_t fevent_spin_lock; bool kickoff_in_progress; unsigned long revalidate_mask; /* for handling internal event thread */ struct sde_crtc_event event_cache[SDE_CRTC_MAX_EVENT_COUNT]; Loading