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Unverified Commit 732e8e41 authored by Andreas Schwab's avatar Andreas Schwab Committed by Palmer Dabbelt
Browse files

RISC-V: properly determine hardware caps 



On the Hifive-U platform, cpu 0 is a masked cpu with less capabilities
than the other cpus.  Ignore it for the purpose of determining the
hardware capabilities of the system.

Signed-off-by: default avatarAndreas Schwab <schwab@suse.de>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent d26c4bbf

arch/riscv/kernel/cpufeature.c

+5 −3
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ bool has_fpu __read_mostly; 


void riscv_fill_hwcap(void)

{

	struct device_node *node;

	struct device_node *node = NULL;

	const char *isa;

	size_t i;

	static unsigned long isa2hwcap[256] = {0};
@@ -44,9 +44,11 @@ void riscv_fill_hwcap(void) 


	/*

	 * We don't support running Linux on hertergenous ISA systems.  For

	 * now, we just check the ISA of the first processor.

	 * now, we just check the ISA of the first "okay" processor.

	 */

	node = of_find_node_by_type(NULL, "cpu");

	while ((node = of_find_node_by_type(node, "cpu")))

		if (riscv_of_processor_hartid(node) >= 0)

			break;

	if (!node) {

		pr_warning("Unable to find \"cpu\" devicetree entry");

		return;