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Unverified Commit d26c4bbf authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

RISC-V: SMP cleanup and new features 

This patch series now has evolved to contain several related changes.

1. Updated the assorted cleanup series by Palmer.
The original cleanup patch series can be found here.
http://lists.infradead.org/pipermail/linux-riscv/2018-August/001232.html



2. Implemented decoupling linux logical CPU ids from hart id.
Some of the work has been inspired from ARM64.
Tested on QEMU & HighFive Unleashed board with/without SMP enabled.

3. Included Anup's cleanup and IPI stat patch.

All the patch series have been combined to avoid conflicts as a lot of
common code is changed different patch sets. Atish has mostly addressed
review comments and fixed checkpatch errors from Palmer's and Anup's
series.

Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parents a6de21ba 8b20d2db

arch/riscv/include/asm/processor.h

+1 −1
Original line number Diff line number Diff line
@@ -88,7 +88,7 @@ static inline void wait_for_interrupt(void) 
}



struct device_node;

extern int riscv_of_processor_hart(struct device_node *node);

int riscv_of_processor_hartid(struct device_node *node);



extern void riscv_fill_hwcap(void);

arch/riscv/include/asm/smp.h

+36 −11
Original line number Diff line number Diff line
@@ -14,16 +14,24 @@ 
#ifndef _ASM_RISCV_SMP_H

#define _ASM_RISCV_SMP_H



/* This both needs asm-offsets.h and is used when generating it. */

#ifndef GENERATING_ASM_OFFSETS

#include <asm/asm-offsets.h>

#endif



#include <linux/cpumask.h>

#include <linux/irqreturn.h>

#include <linux/thread_info.h>



#define INVALID_HARTID ULONG_MAX

/*

 * Mapping between linux logical cpu index and hartid.

 */

extern unsigned long __cpuid_to_hartid_map[NR_CPUS];

#define cpuid_to_hartid_map(cpu)    __cpuid_to_hartid_map[cpu]



struct seq_file;



#ifdef CONFIG_SMP



/* print IPI stats */

void show_ipi_stats(struct seq_file *p, int prec);



/* SMP initialization hook for setup_arch */

void __init setup_smp(void);
@@ -33,14 +41,31 @@ void arch_send_call_function_ipi_mask(struct cpumask *mask); 
/* Hook for the generic smp_call_function_single() routine. */

void arch_send_call_function_single_ipi(int cpu);



int riscv_hartid_to_cpuid(int hartid);

void riscv_cpuid_to_hartid_mask(const struct cpumask *in, struct cpumask *out);



/*

 * This is particularly ugly: it appears we can't actually get the definition

 * of task_struct here, but we need access to the CPU this task is running on.

 * Instead of using C we're using asm-offsets.h to get the current processor

 * ID.

 * Obtains the hart ID of the currently executing task.  This relies on

 * THREAD_INFO_IN_TASK, but we define that unconditionally.

 */

#define raw_smp_processor_id() (*((int*)((char*)get_current() + TASK_TI_CPU)))

#define raw_smp_processor_id() (current_thread_info()->cpu)



#endif /* CONFIG_SMP */

#else



static inline void show_ipi_stats(struct seq_file *p, int prec)

{

}



static inline int riscv_hartid_to_cpuid(int hartid)

{

	return 0;

}



static inline void riscv_cpuid_to_hartid_mask(const struct cpumask *in,

					      struct cpumask *out)

{

	cpumask_set_cpu(cpuid_to_hartid_map(0), out);

}



#endif /* CONFIG_SMP */

#endif /* _ASM_RISCV_SMP_H */

arch/riscv/include/asm/tlbflush.h

+13 −3
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#define _ASM_RISCV_TLBFLUSH_H



#include <linux/mm_types.h>

#include <asm/smp.h>



/*

 * Flush entire local TLB.  'sfence.vma' implicitly fences with the instruction
@@ -49,13 +50,22 @@ static inline void flush_tlb_range(struct vm_area_struct *vma, 


#include <asm/sbi.h>



static inline void remote_sfence_vma(struct cpumask *cmask, unsigned long start,

				     unsigned long size)

{

	struct cpumask hmask;



	cpumask_clear(&hmask);

	riscv_cpuid_to_hartid_mask(cmask, &hmask);

	sbi_remote_sfence_vma(hmask.bits, start, size);

}



#define flush_tlb_all() sbi_remote_sfence_vma(NULL, 0, -1)

#define flush_tlb_page(vma, addr) flush_tlb_range(vma, addr, 0)

#define flush_tlb_range(vma, start, end) \

	sbi_remote_sfence_vma(mm_cpumask((vma)->vm_mm)->bits, \

			      start, (end) - (start))

	remote_sfence_vma(mm_cpumask((vma)->vm_mm), start, (end) - (start))

#define flush_tlb_mm(mm) \

	sbi_remote_sfence_vma(mm_cpumask(mm)->bits, 0, -1)

	remote_sfence_vma(mm_cpumask(mm), 0, -1)



#endif /* CONFIG_SMP */

arch/riscv/kernel/cpu.c

+74 −13
Original line number Diff line number Diff line
@@ -14,9 +14,13 @@ 
#include <linux/init.h>

#include <linux/seq_file.h>

#include <linux/of.h>

#include <asm/smp.h>



/* Return -1 if not a valid hart */

int riscv_of_processor_hart(struct device_node *node)

/*

 * Returns the hart ID of the given device tree node, or -1 if the device tree

 * node isn't a RISC-V hart.

 */

int riscv_of_processor_hartid(struct device_node *node)

{

	const char *isa, *status;

	u32 hart;
@@ -58,6 +62,64 @@ int riscv_of_processor_hart(struct device_node *node) 


#ifdef CONFIG_PROC_FS



static void print_isa(struct seq_file *f, const char *orig_isa)

{

	static const char *ext = "mafdc";

	const char *isa = orig_isa;

	const char *e;



	/*

	 * Linux doesn't support rv32e or rv128i, and we only support booting

	 * kernels on harts with the same ISA that the kernel is compiled for.

	 */

#if defined(CONFIG_32BIT)

	if (strncmp(isa, "rv32i", 5) != 0)

		return;

#elif defined(CONFIG_64BIT)

	if (strncmp(isa, "rv64i", 5) != 0)

		return;

#endif



	/* Print the base ISA, as we already know it's legal. */

	seq_puts(f, "isa\t\t: ");

	seq_write(f, isa, 5);

	isa += 5;



	/*

	 * Check the rest of the ISA string for valid extensions, printing those

	 * we find.  RISC-V ISA strings define an order, so we only print the

	 * extension bits when they're in order.

	 */

	for (e = ext; *e != '\0'; ++e) {

		if (isa[0] == e[0]) {

			seq_write(f, isa, 1);

			isa++;

		}

	}

	seq_puts(f, "\n");



	/*

	 * If we were given an unsupported ISA in the device tree then print

	 * a bit of info describing what went wrong.

	 */

	if (isa[0] != '\0')

		pr_info("unsupported ISA \"%s\" in device tree", orig_isa);

}



static void print_mmu(struct seq_file *f, const char *mmu_type)

{

#if defined(CONFIG_32BIT)

	if (strcmp(mmu_type, "riscv,sv32") != 0)

		return;

#elif defined(CONFIG_64BIT)

	if (strcmp(mmu_type, "riscv,sv39") != 0 &&

	    strcmp(mmu_type, "riscv,sv48") != 0)

		return;

#endif



	seq_printf(f, "mmu\t\t: %s\n", mmu_type+6);

}



static void *c_start(struct seq_file *m, loff_t *pos)

{

	*pos = cpumask_next(*pos - 1, cpu_online_mask);
@@ -78,21 +140,20 @@ static void c_stop(struct seq_file *m, void *v) 


static int c_show(struct seq_file *m, void *v)

{

	unsigned long hart_id = (unsigned long)v - 1;

	struct device_node *node = of_get_cpu_node(hart_id, NULL);

	unsigned long cpu_id = (unsigned long)v - 1;

	struct device_node *node = of_get_cpu_node(cpuid_to_hartid_map(cpu_id),

						   NULL);

	const char *compat, *isa, *mmu;



	seq_printf(m, "hart\t: %lu\n", hart_id);

	if (!of_property_read_string(node, "riscv,isa", &isa)

	    && isa[0] == 'r'

	    && isa[1] == 'v')

		seq_printf(m, "isa\t: %s\n", isa);

	if (!of_property_read_string(node, "mmu-type", &mmu)

	    && !strncmp(mmu, "riscv,", 6))

		seq_printf(m, "mmu\t: %s\n", mmu+6);

	seq_printf(m, "processor\t: %lu\n", cpu_id);

	seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));

	if (!of_property_read_string(node, "riscv,isa", &isa))

		print_isa(m, isa);

	if (!of_property_read_string(node, "mmu-type", &mmu))

		print_mmu(m, mmu);

	if (!of_property_read_string(node, "compatible", &compat)

	    && strcmp(compat, "riscv"))

		seq_printf(m, "uarch\t: %s\n", compat);

		seq_printf(m, "uarch\t\t: %s\n", compat);

	seq_puts(m, "\n");



	return 0;

arch/riscv/kernel/entry.S

+0 −1
Original line number Diff line number Diff line
@@ -168,7 +168,6 @@ ENTRY(handle_exception) 


	/* Handle interrupts */

	move a0, sp /* pt_regs */

	move a1, s4 /* scause */

	tail do_IRQ

1:

	/* Exceptions run with interrupts enabled */