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Commit 72dd2a16 authored by Tao Zhang's avatar Tao Zhang Committed by Mao Jinlong
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coresight: tmc: Set flush cti for both etr and etb



Set flush cti for both etr and etb. Set FlushandStop bit to default
value of FFCR in enablement function. Config the correct trigger number
of flush and reset cti for both etr and etb.

Change-Id: Idee3802e5a69aca521a6259f9936ddb8361a87d4
Signed-off-by: default avatarTao Zhang <taozha@codeaurora.org>
Signed-off-by: default avatarMao Jinlong <jinlmao@codeaurora.org>
parent bd0cb901
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