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Commit 71ffd49c authored by Anuj Phogat's avatar Anuj Phogat Committed by Mika Kuoppala
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drm/i915/icl:Add Wa_1606682166 



Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
Disable the Sampler state prefetch functionality in the SARB by
programming 0xB000[30] to '1'. This is to be done at boot time
and the feature must remain disabled permanently.

Fixes flaky tex-mip-level-selection* piglit tests with Mesa i965
driver.

Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: default avatarAnuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181004182939.7668-6-radhakrishna.sripada@intel.com
parent 0c7d2aed

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -7414,6 +7414,7 @@ enum { 


#define GEN7_SARCHKMD				_MMIO(0xB000)

#define GEN7_DISABLE_DEMAND_PREFETCH		(1 << 31)

#define GEN7_DISABLE_SAMPLER_PREFETCH           (1 << 30)



#define GEN7_L3SQCREG1				_MMIO(0xB010)

#define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000

drivers/gpu/drm/i915/intel_workarounds.c

+2 −1
Original line number Diff line number Diff line
@@ -910,7 +910,8 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv) 
	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))

		I915_WRITE(GEN7_SARCHKMD,

			   I915_READ(GEN7_SARCHKMD) |

			   GEN7_DISABLE_DEMAND_PREFETCH);

			   GEN7_DISABLE_DEMAND_PREFETCH |

			   GEN7_DISABLE_SAMPLER_PREFETCH);

}



void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)