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Commit 0c7d2aed authored by Radhakrishna Sripada's avatar Radhakrishna Sripada Committed by Mika Kuoppala
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drm/i915/icl: Add Wa_1406609255 



Shader feature to prefetch binding tables does not support 16:6 18:8 BTP
formats. Enabling fault handling could result in hangs with faults.
Disabling demand prefetch would disable binding table prefetch.

V2: Fix the stepping rivision to B0(Mika)

References: HSDES#1406609255, HSDES#1406573985
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181004182939.7668-5-radhakrishna.sripada@intel.com
parent f53a70bd

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -7412,6 +7412,9 @@ enum { 
#define GEN9_SLICE_COMMON_ECO_CHICKEN1		_MMIO(0x731c)

#define   GEN11_STATE_CACHE_REDIRECT_TO_CS	(1 << 11)



#define GEN7_SARCHKMD				_MMIO(0xB000)

#define GEN7_DISABLE_DEMAND_PREFETCH		(1 << 31)



#define GEN7_L3SQCREG1				_MMIO(0xB010)

#define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000

drivers/gpu/drm/i915/intel_workarounds.c

+6 −0
Original line number Diff line number Diff line
@@ -905,6 +905,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv) 
	I915_WRITE(GAMT_CHKN_BIT_REG,

		   I915_READ(GAMT_CHKN_BIT_REG) |

		   GAMT_CHKN_DISABLE_L3_COH_PIPE);



	/* Wa_1406609255:icl (pre-prod) */

	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))

		I915_WRITE(GEN7_SARCHKMD,

			   I915_READ(GEN7_SARCHKMD) |

			   GEN7_DISABLE_DEMAND_PREFETCH);

}



void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)