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Commit 70b5f09e authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-next-2019-04-21' of https://gitlab.freedesktop.org/drm/msm into drm-next 



This time around it is a bunch of cleanup and fixes, expanding gpu
"zap" shader support (so we can take the GPU out of secure mode on
boot) to a6xx, and small UABI extension to support robustness (see
mesa MR 673).

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGsHwsEfi4y2LYKSqeqDEYvffwVgKhiP8jHcHpxp13J5LQ@mail.gmail.com
parents 42f1a013 b02872df

Documentation/devicetree/bindings/display/msm/gmu.txt

+8 −2
Original line number Diff line number Diff line
@@ -24,7 +24,10 @@ Required properties: 
   * "cxo"

   * "axi"

   * "mnoc"

- power-domains: should be <&clock_gpucc GPU_CX_GDSC>

- power-domains: should be:

	<&clock_gpucc GPU_CX_GDSC>

	<&clock_gpucc GPU_GX_GDSC>

- power-domain-names: Matching names for the power domains

- iommus: phandle to the adreno iommu

- operating-points-v2: phandle to the OPP operating points
@@ -51,7 +54,10 @@ Example: 
			<&gcc GCC_GPU_MEMNOC_GFX_CLK>;

		clock-names = "gmu", "cxo", "axi", "memnoc";



		power-domains = <&gpucc GPU_CX_GDSC>;

		power-domains = <&gpucc GPU_CX_GDSC>,

				<&gpucc GPU_GX_GDSC>;

		power-domain-names = "cx", "gx";



		iommus = <&adreno_smmu 5>;



		operating-points-v2 = <&gmu_opp_table>;

Documentation/devicetree/bindings/display/msm/gpu.txt

+11 −0
Original line number Diff line number Diff line
@@ -22,9 +22,14 @@ Required properties: 
   - qcom,adreno-630.2

- iommus: optional phandle to an adreno iommu instance

- operating-points-v2: optional phandle to the OPP operating points

- interconnects: optional phandle to an interconnect provider.  See

  ../interconnect/interconnect.txt for details.

- qcom,gmu: For GMU attached devices a phandle to the GMU device that will

  control the power for the GPU. Applicable targets:

    - qcom,adreno-630.2

- zap-shader: For a5xx and a6xx devices this node contains a memory-region that

  points to reserved memory to store the zap shader that can be used to help

  bring the GPU out of secure mode.



Example 3xx/4xx/a5xx:
@@ -70,6 +75,12 @@ Example a6xx (with GMU): 


		operating-points-v2 = <&gpu_opp_table>;



		interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;



		qcom,gmu = <&gmu>;



		zap-shader {

			memory-region = <&zap_shader_region>;

		};

	};

};

drivers/gpu/drm/msm/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -21,6 +21,11 @@ config DRM_MSM 
	help

	  DRM/KMS driver for MSM/snapdragon.



config DRM_MSM_GPU_STATE

	bool

	depends on DRM_MSM && (DEBUG_FS || DEV_COREDUMP)

	default y



config DRM_MSM_REGISTER_LOGGING

	bool "MSM DRM register logging"

	depends on DRM_MSM

drivers/gpu/drm/msm/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -15,7 +15,6 @@ msm-y := \ 
	adreno/a6xx_gpu.o \

	adreno/a6xx_gmu.o \

	adreno/a6xx_hfi.o \

	adreno/a6xx_gpu_state.o \

	hdmi/hdmi.o \

	hdmi/hdmi_audio.o \

	hdmi/hdmi_bridge.o \
@@ -96,6 +95,8 @@ msm-y := \ 


msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o



msm-$(CONFIG_DRM_MSM_GPU_STATE)	+= adreno/a6xx_gpu_state.o



msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o

msm-$(CONFIG_COMMON_CLK) += disp/mdp4/mdp4_lvds_pll.o

msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_pll_8960.o

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+1 −108
Original line number Diff line number Diff line
@@ -15,9 +15,6 @@ 
#include <linux/types.h>

#include <linux/cpumask.h>

#include <linux/qcom_scm.h>

#include <linux/dma-mapping.h>

#include <linux/of_address.h>

#include <linux/soc/qcom/mdt_loader.h>

#include <linux/pm_opp.h>

#include <linux/nvmem-consumer.h>

#include <linux/slab.h>
@@ -30,94 +27,6 @@ static void a5xx_dump(struct msm_gpu *gpu); 


#define GPU_PAS_ID 13



static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname)

{

	struct device *dev = &gpu->pdev->dev;

	const struct firmware *fw;

	struct device_node *np;

	struct resource r;

	phys_addr_t mem_phys;

	ssize_t mem_size;

	void *mem_region = NULL;

	int ret;



	if (!IS_ENABLED(CONFIG_ARCH_QCOM))

		return -EINVAL;



	np = of_get_child_by_name(dev->of_node, "zap-shader");

	if (!np)

		return -ENODEV;



	np = of_parse_phandle(np, "memory-region", 0);

	if (!np)

		return -EINVAL;



	ret = of_address_to_resource(np, 0, &r);

	if (ret)

		return ret;



	mem_phys = r.start;

	mem_size = resource_size(&r);



	/* Request the MDT file for the firmware */

	fw = adreno_request_fw(to_adreno_gpu(gpu), fwname);

	if (IS_ERR(fw)) {

		DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname);

		return PTR_ERR(fw);

	}



	/* Figure out how much memory we need */

	mem_size = qcom_mdt_get_size(fw);

	if (mem_size < 0) {

		ret = mem_size;

		goto out;

	}



	/* Allocate memory for the firmware image */

	mem_region = memremap(mem_phys, mem_size,  MEMREMAP_WC);

	if (!mem_region) {

		ret = -ENOMEM;

		goto out;

	}



	/*

	 * Load the rest of the MDT

	 *

	 * Note that we could be dealing with two different paths, since

	 * with upstream linux-firmware it would be in a qcom/ subdir..

	 * adreno_request_fw() handles this, but qcom_mdt_load() does

	 * not.  But since we've already gotten thru adreno_request_fw()

	 * we know which of the two cases it is:

	 */

	if (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY) {

		ret = qcom_mdt_load(dev, fw, fwname, GPU_PAS_ID,

				mem_region, mem_phys, mem_size, NULL);

	} else {

		char *newname;



		newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);



		ret = qcom_mdt_load(dev, fw, newname, GPU_PAS_ID,

				mem_region, mem_phys, mem_size, NULL);

		kfree(newname);

	}

	if (ret)

		goto out;



	/* Send the image to the secure world */

	ret = qcom_scm_pas_auth_and_reset(GPU_PAS_ID);

	if (ret)

		DRM_DEV_ERROR(dev, "Unable to authorize the image\n");



out:

	if (mem_region)

		memunmap(mem_region);



	release_firmware(fw);



	return ret;

}



static void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)

{

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -563,8 +472,6 @@ static int a5xx_zap_shader_resume(struct msm_gpu *gpu) 
static int a5xx_zap_shader_init(struct msm_gpu *gpu)

{

	static bool loaded;

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);

	struct platform_device *pdev = gpu->pdev;

	int ret;



	/*
@@ -574,23 +481,9 @@ static int a5xx_zap_shader_init(struct msm_gpu *gpu) 
	if (loaded)

		return a5xx_zap_shader_resume(gpu);



	/* We need SCM to be able to load the firmware */

	if (!qcom_scm_is_available()) {

		DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n");

		return -EPROBE_DEFER;

	}



	/* Each GPU has a target specific zap shader firmware name to use */

	if (!adreno_gpu->info->zapfw) {

		DRM_DEV_ERROR(&pdev->dev,

			"Zap shader firmware file not specified for this target\n");

		return -ENODEV;

	}



	ret = zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw);

	ret = adreno_zap_shader_load(gpu, GPU_PAS_ID);



	loaded = !ret;



	return ret;

}