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Commit 42f1a013 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-5.2' of git://people.freedesktop.org/~agd5f/linux into drm-next 



- Add the amdgpu specific bits for timeline support
- Add internal interfaces for xgmi pstate support
- DC Z ordering fixes for planes
- Add support for NV12 planes in DC
- Add colorspace properties for planes in DC
- eDP optimizations if the GOP driver already initialized eDP
- DC bandwidth validation tracing support

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190419150034.3473-1-alexander.deucher@amd.com
parents 6e865c72 f55be0be

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+8 −2
Original line number Diff line number Diff line
@@ -436,6 +436,12 @@ struct amdgpu_cs_chunk { 
	void			*kdata;

};



struct amdgpu_cs_post_dep {

	struct drm_syncobj *syncobj;

	struct dma_fence_chain *chain;

	u64 point;

};



struct amdgpu_cs_parser {

	struct amdgpu_device	*adev;

	struct drm_file		*filp;
@@ -465,8 +471,8 @@ struct amdgpu_cs_parser { 
	/* user fence */

	struct amdgpu_bo_list_entry	uf_entry;



	unsigned num_post_dep_syncobjs;

	struct drm_syncobj **post_dep_syncobjs;

	unsigned			num_post_deps;

	struct amdgpu_cs_post_dep	*post_deps;

};



static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+128 −24
Original line number Diff line number Diff line
@@ -215,6 +215,8 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs 
		case AMDGPU_CHUNK_ID_SYNCOBJ_IN:

		case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:

		case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:

		case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:

		case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:

			break;



		default:
@@ -804,9 +806,11 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, 
		ttm_eu_backoff_reservation(&parser->ticket,

					   &parser->validated);



	for (i = 0; i < parser->num_post_dep_syncobjs; i++)

		drm_syncobj_put(parser->post_dep_syncobjs[i]);

	kfree(parser->post_dep_syncobjs);

	for (i = 0; i < parser->num_post_deps; i++) {

		drm_syncobj_put(parser->post_deps[i].syncobj);

		kfree(parser->post_deps[i].chain);

	}

	kfree(parser->post_deps);



	dma_fence_put(parser->fence);
@@ -1117,13 +1121,18 @@ static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p, 
}



static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,

						 uint32_t handle)

						 uint32_t handle, u64 point,

						 u64 flags)

{

	int r;

	struct dma_fence *fence;

	r = drm_syncobj_find_fence(p->filp, handle, 0, 0, &fence);

	if (r)

	int r;



	r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);

	if (r) {

		DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",

			  handle, point, r);

		return r;

	}



	r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);

	dma_fence_put(fence);
@@ -1134,46 +1143,118 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p, 
static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,

					    struct amdgpu_cs_chunk *chunk)

{

	struct drm_amdgpu_cs_chunk_sem *deps;

	unsigned num_deps;

	int i, r;

	struct drm_amdgpu_cs_chunk_sem *deps;



	deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;

	num_deps = chunk->length_dw * 4 /

		sizeof(struct drm_amdgpu_cs_chunk_sem);

	for (i = 0; i < num_deps; ++i) {

		r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle,

							  0, 0);

		if (r)

			return r;

	}



	return 0;

}





static int amdgpu_cs_process_syncobj_timeline_in_dep(struct amdgpu_cs_parser *p,

						     struct amdgpu_cs_chunk *chunk)

{

	struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;

	unsigned num_deps;

	int i, r;



	syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;

	num_deps = chunk->length_dw * 4 /

		sizeof(struct drm_amdgpu_cs_chunk_syncobj);

	for (i = 0; i < num_deps; ++i) {

		r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);

		r = amdgpu_syncobj_lookup_and_add_to_sync(p,

							  syncobj_deps[i].handle,

							  syncobj_deps[i].point,

							  syncobj_deps[i].flags);

		if (r)

			return r;

	}



	return 0;

}



static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,

					     struct amdgpu_cs_chunk *chunk)

{

	struct drm_amdgpu_cs_chunk_sem *deps;

	unsigned num_deps;

	int i;

	struct drm_amdgpu_cs_chunk_sem *deps;



	deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;

	num_deps = chunk->length_dw * 4 /

		sizeof(struct drm_amdgpu_cs_chunk_sem);



	p->post_dep_syncobjs = kmalloc_array(num_deps,

					     sizeof(struct drm_syncobj *),

	p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),

				     GFP_KERNEL);

	p->num_post_deps = 0;



	if (!p->post_deps)

		return -ENOMEM;





	for (i = 0; i < num_deps; ++i) {

		p->post_deps[i].syncobj =

			drm_syncobj_find(p->filp, deps[i].handle);

		if (!p->post_deps[i].syncobj)

			return -EINVAL;

		p->post_deps[i].chain = NULL;

		p->post_deps[i].point = 0;

		p->num_post_deps++;

	}



	return 0;

}





static int amdgpu_cs_process_syncobj_timeline_out_dep(struct amdgpu_cs_parser *p,

						      struct amdgpu_cs_chunk

						      *chunk)

{

	struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;

	unsigned num_deps;

	int i;



	syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;

	num_deps = chunk->length_dw * 4 /

		sizeof(struct drm_amdgpu_cs_chunk_syncobj);



	p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),

				     GFP_KERNEL);

	p->num_post_dep_syncobjs = 0;

	p->num_post_deps = 0;



	if (!p->post_dep_syncobjs)

	if (!p->post_deps)

		return -ENOMEM;



	for (i = 0; i < num_deps; ++i) {

		p->post_dep_syncobjs[i] = drm_syncobj_find(p->filp, deps[i].handle);

		if (!p->post_dep_syncobjs[i])

		struct amdgpu_cs_post_dep *dep = &p->post_deps[i];



		dep->chain = NULL;

		if (syncobj_deps[i].point) {

			dep->chain = kmalloc(sizeof(*dep->chain), GFP_KERNEL);

			if (!dep->chain)

				return -ENOMEM;

		}



		dep->syncobj = drm_syncobj_find(p->filp,

						syncobj_deps[i].handle);

		if (!dep->syncobj) {

			kfree(dep->chain);

			return -EINVAL;

		p->num_post_dep_syncobjs++;

		}

		dep->point = syncobj_deps[i].point;

		p->num_post_deps++;

	}



	return 0;

}
@@ -1187,19 +1268,33 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev, 


		chunk = &p->chunks[i];



		if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES ||

		    chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {

		switch (chunk->chunk_id) {

		case AMDGPU_CHUNK_ID_DEPENDENCIES:

		case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:

			r = amdgpu_cs_process_fence_dep(p, chunk);

			if (r)

				return r;

		} else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) {

			break;

		case AMDGPU_CHUNK_ID_SYNCOBJ_IN:

			r = amdgpu_cs_process_syncobj_in_dep(p, chunk);

			if (r)

				return r;

		} else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_OUT) {

			break;

		case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:

			r = amdgpu_cs_process_syncobj_out_dep(p, chunk);

			if (r)

				return r;

			break;

		case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:

			r = amdgpu_cs_process_syncobj_timeline_in_dep(p, chunk);

			if (r)

				return r;

			break;

		case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:

			r = amdgpu_cs_process_syncobj_timeline_out_dep(p, chunk);

			if (r)

				return r;

			break;

		}

	}
@@ -1210,8 +1305,17 @@ static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p) 
{

	int i;



	for (i = 0; i < p->num_post_dep_syncobjs; ++i)

		drm_syncobj_replace_fence(p->post_dep_syncobjs[i], p->fence);

	for (i = 0; i < p->num_post_deps; ++i) {

		if (p->post_deps[i].chain && p->post_deps[i].point) {

			drm_syncobj_add_point(p->post_deps[i].syncobj,

					      p->post_deps[i].chain,

					      p->fence, p->post_deps[i].point);

			p->post_deps[i].chain = NULL;

		} else {

			drm_syncobj_replace_fence(p->post_deps[i].syncobj,

						  p->fence);

		}

	}

}



static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -75,9 +75,10 @@ 
 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID

 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.

 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC

 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.

 */

#define KMS_DRIVER_MAJOR	3

#define KMS_DRIVER_MINOR	31

#define KMS_DRIVER_MINOR	32

#define KMS_DRIVER_PATCHLEVEL	0



int amdgpu_vram_limit = 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

+17 −7
Original line number Diff line number Diff line
@@ -136,8 +136,9 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, 
{

	struct amdgpu_device *adev = ring->adev;

	struct amdgpu_fence *fence;

	struct dma_fence *old, **ptr;

	struct dma_fence __rcu **ptr;

	uint32_t seq;

	int r;



	fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);

	if (fence == NULL)
@@ -153,15 +154,24 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, 
			       seq, flags | AMDGPU_FENCE_FLAG_INT);



	ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];

	if (unlikely(rcu_dereference_protected(*ptr, 1))) {

		struct dma_fence *old;



		rcu_read_lock();

		old = dma_fence_get_rcu_safe(ptr);

		rcu_read_unlock();



		if (old) {

			r = dma_fence_wait(old, false);

			dma_fence_put(old);

			if (r)

				return r;

		}

	}



	/* This function can't be called concurrently anyway, otherwise

	 * emitting the fence would mess up the hardware ring buffer.

	 */

	old = rcu_dereference_protected(*ptr, 1);

	if (old && !dma_fence_is_signaled(old)) {

		DRM_INFO("rcu slot is busy\n");

		dma_fence_wait(old, false);

	}



	rcu_assign_pointer(*ptr, dma_fence_get(&fence->base));



	*f = &fence->base;

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

+12 −1
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
#include <linux/list.h>

#include "amdgpu.h"

#include "amdgpu_xgmi.h"

#include "amdgpu_smu.h"





static DEFINE_MUTEX(xgmi_mutex);
@@ -216,7 +217,17 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate) 


	if (hive->pstate == pstate)

		return 0;

	/* Todo : sent the message to SMU for pstate change */



	dev_dbg(adev->dev, "Set xgmi pstate %d.\n", pstate);



	if (is_support_sw_smu(adev))

		ret = smu_set_xgmi_pstate(&adev->smu, pstate);

	if (ret)

		dev_err(adev->dev,

			"XGMI: Set pstate failure on device %llx, hive %llx, ret %d",

			adev->gmc.xgmi.node_id,

			adev->gmc.xgmi.hive_id, ret);



	return ret;

}