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Commit 70661b74 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "cnss2: Fix SBL logging for invalid log location address"

parents 901facd8 f92b9ec2

drivers/net/wireless/cnss2/pci.c

+21 −13
Original line number Original line Diff line number Diff line
@@ -1705,6 +1705,7 @@ static void cnss_pci_dump_bl_sram_mem(struct cnss_pci_data *pci_priv) 
{

{

	int i;

	int i;

	u32 mem_addr, val, pbl_stage, sbl_log_start, sbl_log_size;

	u32 mem_addr, val, pbl_stage, sbl_log_start, sbl_log_size;

	u32 pbl_wlan_boot_cfg, pbl_bootstrap_status;

	struct cnss_plat_data *plat_priv = pci_priv->plat_priv;

	struct cnss_plat_data *plat_priv = pci_priv->plat_priv;





	if (plat_priv->device_id != QCA6490_DEVICE_ID)

	if (plat_priv->device_id != QCA6490_DEVICE_ID)
@@ -1718,8 +1719,14 @@ static void cnss_pci_dump_bl_sram_mem(struct cnss_pci_data *pci_priv) 
			  &sbl_log_start);

			  &sbl_log_start);

	cnss_pci_reg_read(pci_priv, QCA6490_PCIE_BHI_ERRDBG3_REG,

	cnss_pci_reg_read(pci_priv, QCA6490_PCIE_BHI_ERRDBG3_REG,

			  &sbl_log_size);

			  &sbl_log_size);

	cnss_pr_dbg("TCSR_PBL_LOGGING: 0x%08x PCIE_BHI_ERRDBG: 0x%08x 0x%08x",

	cnss_pci_reg_read(pci_priv, QCA6490_PBL_WLAN_BOOT_CFG,

			  &pbl_wlan_boot_cfg);

	cnss_pci_reg_read(pci_priv, QCA6490_PBL_BOOTSTRAP_STATUS,

			  &pbl_bootstrap_status);

	cnss_pr_dbg("TCSR_PBL_LOGGING: 0x%08x PCIE_BHI_ERRDBG: Start: 0x%08x Size:0x%08x",

		    pbl_stage, sbl_log_start, sbl_log_size);

		    pbl_stage, sbl_log_start, sbl_log_size);

	cnss_pr_dbg("PBL_WLAN_BOOT_CFG: 0x%08x PBL_BOOTSTRAP_STATUS: 0x%08x",

		    pbl_wlan_boot_cfg, pbl_bootstrap_status);





	cnss_pr_dbg("Dumping PBL log data");

	cnss_pr_dbg("Dumping PBL log data");

	/* cnss_pci_reg_read provides 32bit register values */

	/* cnss_pci_reg_read provides 32bit register values */
@@ -1730,28 +1737,30 @@ static void cnss_pci_dump_bl_sram_mem(struct cnss_pci_data *pci_priv) 
		cnss_pr_dbg("SRAM[0x%x] = 0x%x\n", mem_addr, val);

		cnss_pr_dbg("SRAM[0x%x] = 0x%x\n", mem_addr, val);

	}

	}





	sbl_log_size = (sbl_log_size > QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE ?

			QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE : sbl_log_size);

	if (plat_priv->device_version.major_version == FW_V2_NUMBER) {

	if (plat_priv->device_version.major_version == FW_V2_NUMBER) {

		if (sbl_log_start > QCA6490_V2_SBL_DATA_START &&

		if (sbl_log_start < QCA6490_V2_SBL_DATA_START ||

		    (sbl_log_start + sbl_log_size) < QCA6490_V2_SBL_DATA_END)

		    sbl_log_start > QCA6490_V2_SBL_DATA_END ||

			goto dump_sbl_log;

		    (sbl_log_start + sbl_log_size) > QCA6490_V2_SBL_DATA_END)

			goto out;

	} else {

	} else {

		if (sbl_log_start > QCA6490_V1_SBL_DATA_START &&

		if (sbl_log_start < QCA6490_V1_SBL_DATA_START ||

		    (sbl_log_start + sbl_log_size) < QCA6490_V1_SBL_DATA_END)

		    sbl_log_start > QCA6490_V1_SBL_DATA_END ||

			goto dump_sbl_log;

		    (sbl_log_start + sbl_log_size) > QCA6490_V1_SBL_DATA_END)

			goto out;

	}

	}

	cnss_pr_err("Invalid SBL log data");

	return;





dump_sbl_log:

	cnss_pr_dbg("Dumping SBL log data");

	cnss_pr_dbg("Dumping SBL log data");

	sbl_log_size = (sbl_log_size > QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE ?

			QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE : sbl_log_size);

	for (i = 0; i < sbl_log_size; i += sizeof(val)) {

	for (i = 0; i < sbl_log_size; i += sizeof(val)) {

		mem_addr = sbl_log_start + i;

		mem_addr = sbl_log_start + i;

		if (cnss_pci_reg_read(pci_priv, mem_addr, &val))

		if (cnss_pci_reg_read(pci_priv, mem_addr, &val))

			break;

			break;

		cnss_pr_dbg("SRAM[0x%x] = 0x%x\n", mem_addr, val);

		cnss_pr_dbg("SRAM[0x%x] = 0x%x\n", mem_addr, val);

	}

	}

	return;

out:

	cnss_pr_err("Invalid SBL log data");

}

}





static int cnss_qca6174_powerup(struct cnss_pci_data *pci_priv)

static int cnss_qca6174_powerup(struct cnss_pci_data *pci_priv)
@@ -3918,7 +3927,6 @@ int cnss_pci_force_fw_assert_hdlr(struct cnss_pci_data *pci_priv) 
	cnss_auto_resume(&pci_priv->pci_dev->dev);

	cnss_auto_resume(&pci_priv->pci_dev->dev);

	cnss_pci_dump_misc_reg(pci_priv);

	cnss_pci_dump_misc_reg(pci_priv);

	cnss_pci_dump_shadow_reg(pci_priv);

	cnss_pci_dump_shadow_reg(pci_priv);

	cnss_pci_dump_bl_sram_mem(pci_priv);





	ret = cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_TRIGGER_RDDM);

	ret = cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_TRIGGER_RDDM);

	if (ret) {

	if (ret) {

drivers/net/wireless/cnss2/reg.h

+2 −1
Original line number Original line Diff line number Diff line
@@ -277,5 +277,6 @@ 
#define QCA6490_TCSR_PBL_LOGGING_REG 0x01B000F8

#define QCA6490_TCSR_PBL_LOGGING_REG 0x01B000F8

#define QCA6490_PCIE_BHI_ERRDBG2_REG 0x01E0E238

#define QCA6490_PCIE_BHI_ERRDBG2_REG 0x01E0E238

#define QCA6490_PCIE_BHI_ERRDBG3_REG 0x01E0E23C

#define QCA6490_PCIE_BHI_ERRDBG3_REG 0x01E0E23C



#define QCA6490_PBL_WLAN_BOOT_CFG 0x01E22B34

#define QCA6490_PBL_BOOTSTRAP_STATUS 0x01910008

#endif
 
#endif