Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f92b9ec2 authored by Manikandan Mohan's avatar Manikandan Mohan
Browse files

cnss2: Fix SBL logging for invalid log location address



Fix SBL log dump for invalid log location address. Also remove
SBL / PBL dumping from forced FW assert handler as it is
needed only to debug pre mission mode failures.

Change-Id: I9e7f84ca8f0b9afc8c9d035f068169c03c3be5f9
Signed-off-by: default avatarManikandan Mohan <manikand@codeaurora.org>
parent e61e6037
Loading
Loading
Loading
Loading
+14 −13
Original line number Diff line number Diff line
@@ -1738,7 +1738,7 @@ static void cnss_pci_dump_bl_sram_mem(struct cnss_pci_data *pci_priv)
			  &pbl_wlan_boot_cfg);
	cnss_pci_reg_read(pci_priv, QCA6490_PBL_BOOTSTRAP_STATUS,
			  &pbl_bootstrap_status);
	cnss_pr_dbg("TCSR_PBL_LOGGING: 0x%08x PCIE_BHI_ERRDBG: 0x%08x 0x%08x",
	cnss_pr_dbg("TCSR_PBL_LOGGING: 0x%08x PCIE_BHI_ERRDBG: Start: 0x%08x Size:0x%08x",
		    pbl_stage, sbl_log_start, sbl_log_size);
	cnss_pr_dbg("PBL_WLAN_BOOT_CFG: 0x%08x PBL_BOOTSTRAP_STATUS: 0x%08x",
		    pbl_wlan_boot_cfg, pbl_bootstrap_status);
@@ -1752,28 +1752,30 @@ static void cnss_pci_dump_bl_sram_mem(struct cnss_pci_data *pci_priv)
		cnss_pr_dbg("SRAM[0x%x] = 0x%x\n", mem_addr, val);
	}

	sbl_log_size = (sbl_log_size > QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE ?
			QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE : sbl_log_size);
	if (plat_priv->device_version.major_version == FW_V2_NUMBER) {
		if (sbl_log_start > QCA6490_V2_SBL_DATA_START &&
		    (sbl_log_start + sbl_log_size) < QCA6490_V2_SBL_DATA_END)
			goto dump_sbl_log;
		if (sbl_log_start < QCA6490_V2_SBL_DATA_START ||
		    sbl_log_start > QCA6490_V2_SBL_DATA_END ||
		    (sbl_log_start + sbl_log_size) > QCA6490_V2_SBL_DATA_END)
			goto out;
	} else {
		if (sbl_log_start > QCA6490_V1_SBL_DATA_START &&
		    (sbl_log_start + sbl_log_size) < QCA6490_V1_SBL_DATA_END)
			goto dump_sbl_log;
		if (sbl_log_start < QCA6490_V1_SBL_DATA_START ||
		    sbl_log_start > QCA6490_V1_SBL_DATA_END ||
		    (sbl_log_start + sbl_log_size) > QCA6490_V1_SBL_DATA_END)
			goto out;
	}
	cnss_pr_err("Invalid SBL log data");
	return;

dump_sbl_log:
	cnss_pr_dbg("Dumping SBL log data");
	sbl_log_size = (sbl_log_size > QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE ?
			QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE : sbl_log_size);
	for (i = 0; i < sbl_log_size; i += sizeof(val)) {
		mem_addr = sbl_log_start + i;
		if (cnss_pci_reg_read(pci_priv, mem_addr, &val))
			break;
		cnss_pr_dbg("SRAM[0x%x] = 0x%x\n", mem_addr, val);
	}
	return;
out:
	cnss_pr_err("Invalid SBL log data");
}

static int cnss_qca6174_powerup(struct cnss_pci_data *pci_priv)
@@ -3924,7 +3926,6 @@ int cnss_pci_force_fw_assert_hdlr(struct cnss_pci_data *pci_priv)
	cnss_auto_resume(&pci_priv->pci_dev->dev);
	cnss_pci_dump_misc_reg(pci_priv);
	cnss_pci_dump_shadow_reg(pci_priv);
	cnss_pci_dump_bl_sram_mem(pci_priv);

	ret = cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_TRIGGER_RDDM);
	if (ret) {