Loading qcom/yupik.dtsi +4 −5 Original line number Diff line number Diff line Loading @@ -1452,7 +1452,9 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; }; Loading @@ -1462,10 +1464,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, <&rpmhcc RPMH_IPA_CLK>; clocks = <&rpmhcc RPMH_IPA_CLK>; }; mmss_noc: interconnect@1740000 { Loading Loading
qcom/yupik.dtsi +4 −5 Original line number Diff line number Diff line Loading @@ -1452,7 +1452,9 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; }; Loading @@ -1462,10 +1464,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, <&rpmhcc RPMH_IPA_CLK>; clocks = <&rpmhcc RPMH_IPA_CLK>; }; mmss_noc: interconnect@1740000 { Loading