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Commit 95cfc3de authored by Odelu Kukatla's avatar Odelu Kukatla Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add handles for PCIE clocks for Yupik 

PCIE cocks need to be enabled for QoS settings programming,
so add PCIE clock handles.

Change-Id: Iba060132a1645fb63dd75680b9a56d129966c1a0
parent 31601896

qcom/yupik.dtsi

+4 −5
Original line number Original line Diff line number Diff line
@@ -1450,7 +1450,9 @@ 
		#interconnect-cells = <1>;

		#interconnect-cells = <1>;

		qcom,bcm-voter-names = "hlos";

		qcom,bcm-voter-names = "hlos";

		qcom,bcm-voters = <&apps_bcm_voter>;

		qcom,bcm-voters = <&apps_bcm_voter>;

		clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

		clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,

			<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,

			<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

			<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;

			<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;

	};

	};
@@ -1460,10 +1462,7 @@ 
		#interconnect-cells = <1>;

		#interconnect-cells = <1>;

		qcom,bcm-voter-names = "hlos";

		qcom,bcm-voter-names = "hlos";

		qcom,bcm-voters = <&apps_bcm_voter>;

		qcom,bcm-voters = <&apps_bcm_voter>;

		clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

		clocks = <&rpmhcc RPMH_IPA_CLK>;

			<&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,

			<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,

			<&rpmhcc RPMH_IPA_CLK>;

	};

	};





	mmss_noc: interconnect@1740000 {

	mmss_noc: interconnect@1740000 {