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Commit 6bcc0ef1 authored by Naveen Yadav's avatar Naveen Yadav
Browse files

dt-bindings: clk: Add PCIe pipe and USB3 pipe clocks 



Add PCIe pipe and USB3 pipe clock bindings for sdxlemur.

Change-Id: If81419ba2751c728e2cd0b1e3cab8a1196e81aa9
Signed-off-by: default avatarNaveen Yadav <naveenky@codeaurora.org>
parent f0e66e89

include/dt-bindings/clock/qcom,gcc-sdxlemur.h

+39 −36
Original line number Diff line number Diff line
@@ -49,42 +49,45 @@ 
#define GCC_GP3_CLK_SRC						39

#define GCC_PCIE_0_CLKREF_EN					40

#define GCC_PCIE_AUX_CLK					41

#define GCC_PCIE_AUX_PHY_CLK_SRC				42

#define GCC_PCIE_CFG_AHB_CLK					43

#define GCC_PCIE_MSTR_AXI_CLK					44

#define GCC_PCIE_PIPE_CLK					45

#define GCC_PCIE_RCHNG_PHY_CLK					46

#define GCC_PCIE_RCHNG_PHY_CLK_SRC				47

#define GCC_PCIE_SLEEP_CLK					48

#define GCC_PCIE_SLV_AXI_CLK					49

#define GCC_PCIE_SLV_Q2A_AXI_CLK				50

#define GCC_PDM2_CLK						51

#define GCC_PDM2_CLK_SRC					52

#define GCC_PDM_AHB_CLK						53

#define GCC_PDM_XO4_CLK						54

#define GCC_RX1_USB2_CLKREF_EN					55

#define GCC_SDCC1_AHB_CLK					56

#define GCC_SDCC1_APPS_CLK					57

#define GCC_SDCC1_APPS_CLK_SRC					58

#define GCC_SPMI_FETCHER_AHB_CLK				59

#define GCC_SPMI_FETCHER_CLK					60

#define GCC_SPMI_FETCHER_CLK_SRC				61

#define GCC_SYS_NOC_CPUSS_AHB_CLK				62

#define GCC_USB30_MASTER_CLK					63

#define GCC_USB30_MASTER_CLK_SRC				64

#define GCC_USB30_MOCK_UTMI_CLK					65

#define GCC_USB30_MOCK_UTMI_CLK_SRC				66

#define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC			67

#define GCC_USB30_MSTR_AXI_CLK					68

#define GCC_USB30_SLEEP_CLK					69

#define GCC_USB30_SLV_AHB_CLK					70

#define GCC_USB3_PHY_AUX_CLK					71

#define GCC_USB3_PHY_AUX_CLK_SRC				72

#define GCC_USB3_PHY_PIPE_CLK					73

#define GCC_USB3_PRIM_CLKREF_EN					74

#define GCC_USB_PHY_CFG_AHB2PHY_CLK				75

#define GCC_XO_DIV4_CLK						76

#define GCC_XO_PCIE_LINK_CLK					77

#define GCC_PCIE_AUX_CLK_SRC					42

#define GCC_PCIE_AUX_PHY_CLK_SRC				43

#define GCC_PCIE_CFG_AHB_CLK					44

#define GCC_PCIE_MSTR_AXI_CLK					45

#define GCC_PCIE_PIPE_CLK					46

#define GCC_PCIE_PIPE_CLK_SRC					47

#define GCC_PCIE_RCHNG_PHY_CLK					48

#define GCC_PCIE_RCHNG_PHY_CLK_SRC				49

#define GCC_PCIE_SLEEP_CLK					50

#define GCC_PCIE_SLV_AXI_CLK					51

#define GCC_PCIE_SLV_Q2A_AXI_CLK				52

#define GCC_PDM2_CLK						53

#define GCC_PDM2_CLK_SRC					54

#define GCC_PDM_AHB_CLK						55

#define GCC_PDM_XO4_CLK						56

#define GCC_RX1_USB2_CLKREF_EN					57

#define GCC_SDCC1_AHB_CLK					58

#define GCC_SDCC1_APPS_CLK					59

#define GCC_SDCC1_APPS_CLK_SRC					60

#define GCC_SPMI_FETCHER_AHB_CLK				61

#define GCC_SPMI_FETCHER_CLK					62

#define GCC_SPMI_FETCHER_CLK_SRC				63

#define GCC_SYS_NOC_CPUSS_AHB_CLK				64

#define GCC_USB30_MASTER_CLK					65

#define GCC_USB30_MASTER_CLK_SRC				66

#define GCC_USB30_MOCK_UTMI_CLK					67

#define GCC_USB30_MOCK_UTMI_CLK_SRC				68

#define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC			69

#define GCC_USB30_MSTR_AXI_CLK					70

#define GCC_USB30_SLEEP_CLK					71

#define GCC_USB30_SLV_AHB_CLK					72

#define GCC_USB3_PHY_AUX_CLK					73

#define GCC_USB3_PHY_AUX_CLK_SRC				74

#define GCC_USB3_PHY_PIPE_CLK					75

#define GCC_USB3_PHY_PIPE_CLK_SRC				76

#define GCC_USB3_PRIM_CLKREF_EN					77

#define GCC_USB_PHY_CFG_AHB2PHY_CLK				78

#define GCC_XO_DIV4_CLK						79

#define GCC_XO_PCIE_LINK_CLK					80



/* GCC resets */

#define GCC_BLSP1_QUP1_BCR					0