Loading arch/arm64/configs/vendor/genericarmv8-64_defconfig +2 −0 Original line number Diff line number Diff line Loading @@ -278,6 +278,8 @@ CONFIG_DEBUG_INFO=y CONFIG_DEBUG_FS=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_PANIC_ON_OOPS=y CONFIG_PANIC_TIMEOUT=-1 # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_PREEMPT is not set CONFIG_STACKTRACE=y Loading arch/arm64/configs/vendor/lahaina_GKI.config +3 −1 Original line number Diff line number Diff line Loading @@ -57,7 +57,7 @@ CONFIG_QCOM_LLCC=m CONFIG_QCOM_LAHAINA_LLCC=m CONFIG_QCOM_SHIMA_LLCC=m CONFIG_QCOM_IPCC=m CONFIG_QCOM_WATCHDOG=m CONFIG_QCOM_WDT_CORE=m CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y CONFIG_QCOM_MEMORY_DUMP_V2=m CONFIG_QCOM_SCM=m Loading Loading @@ -232,3 +232,5 @@ CONFIG_SM_DISPCC_SHIMA=m CONFIG_NETFILTER_XT_MATCH_DSCP=y CONFIG_INCREMENTAL_FS=m CONFIG_QCOM_MICRODUMP=m CONFIG_HH_VIRT_WATCHDOG=m CONFIG_QCOM_SOC_WATCHDOG=m drivers/soc/qcom/Kconfig +68 −8 Original line number Diff line number Diff line Loading @@ -783,18 +783,31 @@ config CDSPRM_VTCM_DYNAMIC_DEBUG enabled, the vtcm partition details are sent to the CDSP via rpmsg channel. config QCOM_WATCHDOG tristate "Qualcomm Watchdog Support" config QCOM_WDT_CORE tristate "Qualcomm Technologies, Inc. Watchdog Support" depends on ARCH_QCOM help This enables the watchdog module. It causes kernel panic if the watchdog times out. It allows for detection of cpu hangs and deadlocks. It does not run during the bootup process, so it will not catch any early lockups. This enables the watchdog framework for Qualcomm Technologies, Inc. devices. It causes a kernel panic if the watchdog times out. It allows for the detection of cpu hangs and deadlocks. It does not run during the bootup process, so it will not catch any early lockups. Enabling this only enables the framework, an individual Qualcomm Technologies, Inc. watchdog module must be loaded along with this for watchdog functionality. config QCOM_SOC_WATCHDOG tristate "Qualcomm Technologies, Inc. Soc Watchdog" depends on QCOM_WDT_CORE help This enables the Qualcomm Technologies, Inc. watchdog module for the Soc. It provides an interface to perform watchdog actions such as setting the bark/bite time and also petting the hardware watchdog. To utilize this the Qualcomm Technologies, Inc. watchdog framework must also be enabled. config QCOM_FORCE_WDOG_BITE_ON_PANIC bool "QCOM force watchdog bite on panic" depends on QCOM_WATCHDOG depends on QCOM_WDT_CORE help This forces a watchdog bite when the device restarts due to a kernel panic. On certain MSM SoCs, Loading @@ -803,7 +816,7 @@ config QCOM_FORCE_WDOG_BITE_ON_PANIC config QCOM_WDOG_BITE_EARLY_PANIC bool "QCOM early panic watchdog bite" depends on QCOM_WATCHDOG && QCOM_FORCE_WDOG_BITE_ON_PANIC depends on QCOM_WDT_CORE && QCOM_FORCE_WDOG_BITE_ON_PANIC help This forces a watchdog bite early in panic sequence. On certain MSM SoCs, this provides us additional debugging information at the Loading @@ -811,6 +824,53 @@ config QCOM_WDOG_BITE_EARLY_PANIC later in panic, which permits more of the restart sequence to run (e.g. more dmesg to flushed to console). config QCOM_WATCHDOG_BARK_TIME depends on QCOM_WDT_CORE int "Qualcomm Technologies, Inc. Watchdog bark time in ms" default 11000 range 11000 11000 help The amount of time, in milliseconds, that should elapse after a watchdog timer reset before a bark interrupt is sent from the watchdog. config QCOM_WATCHDOG_PET_TIME depends on QCOM_WDT_CORE int "Qualcomm Technologies, Inc. Watchdog pet time in ms" default 9360 range 9360 9360 help The amount of time, in milliseconds, that should elapse before a watchdog pet is initiated to reset the watchdog timer to 0. config QCOM_WATCHDOG_IPI_PING depends on QCOM_WDT_CORE bool "Qualcomm Technologies, Inc. Watchdog ipi ping" default y help This boolean flag gives the watchdog driver the ability to send a keep-alive ping to other cpu's if it is set to 1. Otherwise, when it is set to 0 no keep alive pings will be sent. config QCOM_WATCHDOG_WAKEUP_ENABLE depends on QCOM_WDT_CORE bool "Qualcomm Technologies, Inc. Watchdog wakeup enable" default y help This boolean flag allows the non secure watchdog counter to freeze and unfreeze automatically across the system suspend and resume path. config QCOM_WATCHDOG_USERSPACE_PET depends on QCOM_WDT_CORE bool "Qualcomm Technologies, Inc. Watchdog user pet enable" default n help This boolean flag allows enabling the userspace-watchdog feature. This feature requires userspace to pet the watchdog every in an interval that matches the time set in the pet-time config. The feature is supported through device sysfs files. config MSM_SPCOM depends on QCOM_GLINK tristate "Secure Processor Communication over RPMSG" Loading drivers/soc/qcom/Makefile +2 −1 Original line number Diff line number Diff line Loading @@ -74,7 +74,6 @@ ifdef CONFIG_MSM_RPM_SMD obj-$(CONFIG_QTI_RPM_STATS_LOG) += rpm_master_stat.o endif obj-$(CONFIG_QPNP_PBS) += qpnp-pbs.o obj-$(CONFIG_QCOM_WATCHDOG) += qcom_watchdog.o obj-$(CONFIG_MSM_SPCOM) += spcom.o obj-$(CONFIG_QCOM_CDSP_RM) += cdsprm.o obj-$(CONFIG_QCOM_FSA4480_I2C) += fsa4480-i2c.o Loading @@ -85,6 +84,8 @@ obj-$(CONFIG_MSM_QBT_HANDLER) += qbt_handler.o obj-$(CONFIG_QTI_CRYPTO_COMMON) += crypto-qti-common.o obj-$(CONFIG_QTI_CRYPTO_TZ) += crypto-qti-tz.o obj-$(CONFIG_QTI_HW_KEY_MANAGER) += hwkm.o crypto-qti-hwkm.o obj-$(CONFIG_QCOM_WDT_CORE) += qcom_wdt_core.o obj-$(CONFIG_QCOM_SOC_WATCHDOG) += qcom_soc_wdt.o ifdef CONFIG_DEBUG_FS obj-$(CONFIG_MSM_RPM_SMD) += rpm-smd-debug.o endif Loading drivers/soc/qcom/qcom_soc_wdt.c 0 → 100644 +150 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. * */ #include <soc/qcom/watchdog.h> #include <linux/kernel.h> #include <linux/platform_device.h> #include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/io.h> #define WDT0_RST 0x04 #define WDT0_EN 0x08 #define WDT0_STS 0x0C #define WDT0_BARK_TIME 0x10 #define WDT0_BITE_TIME 0x14 #define WDT_HZ 32765 static inline int qcom_soc_set_wdt_bark(u32 time, struct msm_watchdog_data *wdog_dd) { __raw_writel((time * WDT_HZ)/1000, wdog_dd->base + WDT0_BARK_TIME); /* Make sure register write is complete before proceeding */ mb(); return 0; } static inline int qcom_soc_set_wdt_bite(u32 time, struct msm_watchdog_data *wdog_dd) { __raw_writel((time * WDT_HZ)/1000, wdog_dd->base + WDT0_BITE_TIME); /* Make sure register write is complete before proceeding */ mb(); return 0; } static inline int qcom_soc_reset_wdt(struct msm_watchdog_data *wdog_dd) { __raw_writel(1, wdog_dd->base + WDT0_RST); /* Make sure register write is complete before proceeding */ mb(); return 0; } static inline int qcom_soc_enable_wdt(u32 val, struct msm_watchdog_data *wdog_dd) { __raw_writel(val, wdog_dd->base + WDT0_EN); /* Make sure register write is complete before proceeding */ mb(); return 0; } static inline int qcom_soc_disable_wdt(struct msm_watchdog_data *wdog_dd) { __raw_writel(0, wdog_dd->base + WDT0_EN); /* Make sure register write is complete before proceeding */ mb(); return 0; } static inline int qcom_soc_show_wdt_status(struct msm_watchdog_data *wdog_dd) { dev_err(wdog_dd->dev, "Wdog - STS: 0x%x, CTL: 0x%x, BARK TIME: 0x%x, BITE TIME: 0x%x\n", __raw_readl(wdog_dd->base + WDT0_STS), __raw_readl(wdog_dd->base + WDT0_EN), __raw_readl(wdog_dd->base + WDT0_BARK_TIME), __raw_readl(wdog_dd->base + WDT0_BITE_TIME)); return 0; } static struct qcom_wdt_ops qcom_soc_wdt_ops = { .set_bark_time = qcom_soc_set_wdt_bark, .set_bite_time = qcom_soc_set_wdt_bite, .reset_wdt = qcom_soc_reset_wdt, .enable_wdt = qcom_soc_enable_wdt, .disable_wdt = qcom_soc_disable_wdt, .show_wdt_status = qcom_soc_show_wdt_status }; static int qcom_soc_wdt_probe(struct platform_device *pdev) { struct resource *res; struct msm_watchdog_data *wdog_dd; wdog_dd = devm_kzalloc(&pdev->dev, sizeof(*wdog_dd), GFP_KERNEL); if (!wdog_dd) return -ENOMEM; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wdt-base"); if (!res) return -ENODEV; wdog_dd->base = devm_ioremap_resource(&pdev->dev, res); if (!wdog_dd->base) { dev_err(&pdev->dev, "%s cannot map wdog register space\n", __func__); return -ENXIO; } wdog_dd->ops = &qcom_soc_wdt_ops; return qcom_wdt_register(pdev, wdog_dd, "msm-watchdog"); } #ifdef CONFIG_PM_SLEEP static const struct dev_pm_ops qcom_soc_dev_pm_ops = { .suspend_noirq = qcom_wdt_suspend, .resume_noirq = qcom_wdt_resume, }; #else static const struct dev_pm_ops qcom_soc_dev_pm_ops = { }; #endif static const struct of_device_id qcom_soc_match_table[] = { { .compatible = "qcom,msm-watchdog" }, {} }; static struct platform_driver qcom_soc_wdt_driver = { .probe = qcom_soc_wdt_probe, .remove = qcom_wdt_remove, .driver = { .name = "msm_watchdog", .pm = &qcom_soc_dev_pm_ops, .of_match_table = qcom_soc_match_table, }, }; static int __init init_watchdog(void) { return platform_driver_register(&qcom_soc_wdt_driver); } #if IS_MODULE(CONFIG_QCOM_SOC_WATCHDOG) module_init(init_watchdog); #else pure_initcall(init_watchdog); #endif static __exit void exit_watchdog(void) { platform_driver_unregister(&qcom_soc_wdt_driver); } module_exit(exit_watchdog); MODULE_DESCRIPTION("QCOM Soc Watchdog Driver"); MODULE_LICENSE("GPL v2"); Loading
arch/arm64/configs/vendor/genericarmv8-64_defconfig +2 −0 Original line number Diff line number Diff line Loading @@ -278,6 +278,8 @@ CONFIG_DEBUG_INFO=y CONFIG_DEBUG_FS=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_PANIC_ON_OOPS=y CONFIG_PANIC_TIMEOUT=-1 # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_PREEMPT is not set CONFIG_STACKTRACE=y Loading
arch/arm64/configs/vendor/lahaina_GKI.config +3 −1 Original line number Diff line number Diff line Loading @@ -57,7 +57,7 @@ CONFIG_QCOM_LLCC=m CONFIG_QCOM_LAHAINA_LLCC=m CONFIG_QCOM_SHIMA_LLCC=m CONFIG_QCOM_IPCC=m CONFIG_QCOM_WATCHDOG=m CONFIG_QCOM_WDT_CORE=m CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y CONFIG_QCOM_MEMORY_DUMP_V2=m CONFIG_QCOM_SCM=m Loading Loading @@ -232,3 +232,5 @@ CONFIG_SM_DISPCC_SHIMA=m CONFIG_NETFILTER_XT_MATCH_DSCP=y CONFIG_INCREMENTAL_FS=m CONFIG_QCOM_MICRODUMP=m CONFIG_HH_VIRT_WATCHDOG=m CONFIG_QCOM_SOC_WATCHDOG=m
drivers/soc/qcom/Kconfig +68 −8 Original line number Diff line number Diff line Loading @@ -783,18 +783,31 @@ config CDSPRM_VTCM_DYNAMIC_DEBUG enabled, the vtcm partition details are sent to the CDSP via rpmsg channel. config QCOM_WATCHDOG tristate "Qualcomm Watchdog Support" config QCOM_WDT_CORE tristate "Qualcomm Technologies, Inc. Watchdog Support" depends on ARCH_QCOM help This enables the watchdog module. It causes kernel panic if the watchdog times out. It allows for detection of cpu hangs and deadlocks. It does not run during the bootup process, so it will not catch any early lockups. This enables the watchdog framework for Qualcomm Technologies, Inc. devices. It causes a kernel panic if the watchdog times out. It allows for the detection of cpu hangs and deadlocks. It does not run during the bootup process, so it will not catch any early lockups. Enabling this only enables the framework, an individual Qualcomm Technologies, Inc. watchdog module must be loaded along with this for watchdog functionality. config QCOM_SOC_WATCHDOG tristate "Qualcomm Technologies, Inc. Soc Watchdog" depends on QCOM_WDT_CORE help This enables the Qualcomm Technologies, Inc. watchdog module for the Soc. It provides an interface to perform watchdog actions such as setting the bark/bite time and also petting the hardware watchdog. To utilize this the Qualcomm Technologies, Inc. watchdog framework must also be enabled. config QCOM_FORCE_WDOG_BITE_ON_PANIC bool "QCOM force watchdog bite on panic" depends on QCOM_WATCHDOG depends on QCOM_WDT_CORE help This forces a watchdog bite when the device restarts due to a kernel panic. On certain MSM SoCs, Loading @@ -803,7 +816,7 @@ config QCOM_FORCE_WDOG_BITE_ON_PANIC config QCOM_WDOG_BITE_EARLY_PANIC bool "QCOM early panic watchdog bite" depends on QCOM_WATCHDOG && QCOM_FORCE_WDOG_BITE_ON_PANIC depends on QCOM_WDT_CORE && QCOM_FORCE_WDOG_BITE_ON_PANIC help This forces a watchdog bite early in panic sequence. On certain MSM SoCs, this provides us additional debugging information at the Loading @@ -811,6 +824,53 @@ config QCOM_WDOG_BITE_EARLY_PANIC later in panic, which permits more of the restart sequence to run (e.g. more dmesg to flushed to console). config QCOM_WATCHDOG_BARK_TIME depends on QCOM_WDT_CORE int "Qualcomm Technologies, Inc. Watchdog bark time in ms" default 11000 range 11000 11000 help The amount of time, in milliseconds, that should elapse after a watchdog timer reset before a bark interrupt is sent from the watchdog. config QCOM_WATCHDOG_PET_TIME depends on QCOM_WDT_CORE int "Qualcomm Technologies, Inc. Watchdog pet time in ms" default 9360 range 9360 9360 help The amount of time, in milliseconds, that should elapse before a watchdog pet is initiated to reset the watchdog timer to 0. config QCOM_WATCHDOG_IPI_PING depends on QCOM_WDT_CORE bool "Qualcomm Technologies, Inc. Watchdog ipi ping" default y help This boolean flag gives the watchdog driver the ability to send a keep-alive ping to other cpu's if it is set to 1. Otherwise, when it is set to 0 no keep alive pings will be sent. config QCOM_WATCHDOG_WAKEUP_ENABLE depends on QCOM_WDT_CORE bool "Qualcomm Technologies, Inc. Watchdog wakeup enable" default y help This boolean flag allows the non secure watchdog counter to freeze and unfreeze automatically across the system suspend and resume path. config QCOM_WATCHDOG_USERSPACE_PET depends on QCOM_WDT_CORE bool "Qualcomm Technologies, Inc. Watchdog user pet enable" default n help This boolean flag allows enabling the userspace-watchdog feature. This feature requires userspace to pet the watchdog every in an interval that matches the time set in the pet-time config. The feature is supported through device sysfs files. config MSM_SPCOM depends on QCOM_GLINK tristate "Secure Processor Communication over RPMSG" Loading
drivers/soc/qcom/Makefile +2 −1 Original line number Diff line number Diff line Loading @@ -74,7 +74,6 @@ ifdef CONFIG_MSM_RPM_SMD obj-$(CONFIG_QTI_RPM_STATS_LOG) += rpm_master_stat.o endif obj-$(CONFIG_QPNP_PBS) += qpnp-pbs.o obj-$(CONFIG_QCOM_WATCHDOG) += qcom_watchdog.o obj-$(CONFIG_MSM_SPCOM) += spcom.o obj-$(CONFIG_QCOM_CDSP_RM) += cdsprm.o obj-$(CONFIG_QCOM_FSA4480_I2C) += fsa4480-i2c.o Loading @@ -85,6 +84,8 @@ obj-$(CONFIG_MSM_QBT_HANDLER) += qbt_handler.o obj-$(CONFIG_QTI_CRYPTO_COMMON) += crypto-qti-common.o obj-$(CONFIG_QTI_CRYPTO_TZ) += crypto-qti-tz.o obj-$(CONFIG_QTI_HW_KEY_MANAGER) += hwkm.o crypto-qti-hwkm.o obj-$(CONFIG_QCOM_WDT_CORE) += qcom_wdt_core.o obj-$(CONFIG_QCOM_SOC_WATCHDOG) += qcom_soc_wdt.o ifdef CONFIG_DEBUG_FS obj-$(CONFIG_MSM_RPM_SMD) += rpm-smd-debug.o endif Loading
drivers/soc/qcom/qcom_soc_wdt.c 0 → 100644 +150 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. * */ #include <soc/qcom/watchdog.h> #include <linux/kernel.h> #include <linux/platform_device.h> #include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/io.h> #define WDT0_RST 0x04 #define WDT0_EN 0x08 #define WDT0_STS 0x0C #define WDT0_BARK_TIME 0x10 #define WDT0_BITE_TIME 0x14 #define WDT_HZ 32765 static inline int qcom_soc_set_wdt_bark(u32 time, struct msm_watchdog_data *wdog_dd) { __raw_writel((time * WDT_HZ)/1000, wdog_dd->base + WDT0_BARK_TIME); /* Make sure register write is complete before proceeding */ mb(); return 0; } static inline int qcom_soc_set_wdt_bite(u32 time, struct msm_watchdog_data *wdog_dd) { __raw_writel((time * WDT_HZ)/1000, wdog_dd->base + WDT0_BITE_TIME); /* Make sure register write is complete before proceeding */ mb(); return 0; } static inline int qcom_soc_reset_wdt(struct msm_watchdog_data *wdog_dd) { __raw_writel(1, wdog_dd->base + WDT0_RST); /* Make sure register write is complete before proceeding */ mb(); return 0; } static inline int qcom_soc_enable_wdt(u32 val, struct msm_watchdog_data *wdog_dd) { __raw_writel(val, wdog_dd->base + WDT0_EN); /* Make sure register write is complete before proceeding */ mb(); return 0; } static inline int qcom_soc_disable_wdt(struct msm_watchdog_data *wdog_dd) { __raw_writel(0, wdog_dd->base + WDT0_EN); /* Make sure register write is complete before proceeding */ mb(); return 0; } static inline int qcom_soc_show_wdt_status(struct msm_watchdog_data *wdog_dd) { dev_err(wdog_dd->dev, "Wdog - STS: 0x%x, CTL: 0x%x, BARK TIME: 0x%x, BITE TIME: 0x%x\n", __raw_readl(wdog_dd->base + WDT0_STS), __raw_readl(wdog_dd->base + WDT0_EN), __raw_readl(wdog_dd->base + WDT0_BARK_TIME), __raw_readl(wdog_dd->base + WDT0_BITE_TIME)); return 0; } static struct qcom_wdt_ops qcom_soc_wdt_ops = { .set_bark_time = qcom_soc_set_wdt_bark, .set_bite_time = qcom_soc_set_wdt_bite, .reset_wdt = qcom_soc_reset_wdt, .enable_wdt = qcom_soc_enable_wdt, .disable_wdt = qcom_soc_disable_wdt, .show_wdt_status = qcom_soc_show_wdt_status }; static int qcom_soc_wdt_probe(struct platform_device *pdev) { struct resource *res; struct msm_watchdog_data *wdog_dd; wdog_dd = devm_kzalloc(&pdev->dev, sizeof(*wdog_dd), GFP_KERNEL); if (!wdog_dd) return -ENOMEM; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wdt-base"); if (!res) return -ENODEV; wdog_dd->base = devm_ioremap_resource(&pdev->dev, res); if (!wdog_dd->base) { dev_err(&pdev->dev, "%s cannot map wdog register space\n", __func__); return -ENXIO; } wdog_dd->ops = &qcom_soc_wdt_ops; return qcom_wdt_register(pdev, wdog_dd, "msm-watchdog"); } #ifdef CONFIG_PM_SLEEP static const struct dev_pm_ops qcom_soc_dev_pm_ops = { .suspend_noirq = qcom_wdt_suspend, .resume_noirq = qcom_wdt_resume, }; #else static const struct dev_pm_ops qcom_soc_dev_pm_ops = { }; #endif static const struct of_device_id qcom_soc_match_table[] = { { .compatible = "qcom,msm-watchdog" }, {} }; static struct platform_driver qcom_soc_wdt_driver = { .probe = qcom_soc_wdt_probe, .remove = qcom_wdt_remove, .driver = { .name = "msm_watchdog", .pm = &qcom_soc_dev_pm_ops, .of_match_table = qcom_soc_match_table, }, }; static int __init init_watchdog(void) { return platform_driver_register(&qcom_soc_wdt_driver); } #if IS_MODULE(CONFIG_QCOM_SOC_WATCHDOG) module_init(init_watchdog); #else pure_initcall(init_watchdog); #endif static __exit void exit_watchdog(void) { platform_driver_unregister(&qcom_soc_wdt_driver); } module_exit(exit_watchdog); MODULE_DESCRIPTION("QCOM Soc Watchdog Driver"); MODULE_LICENSE("GPL v2");
