Merge "ARM: dts: msm: Add ice core clock node for shima"

				<GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "hc_irq", "pwr_irq";

		clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;

		clock-names = "core", "iface";

		clocks = <&gcc GCC_SDCC1_APPS_CLK>,

			<&gcc GCC_SDCC1_AHB_CLK>,

			<&gcc GCC_SDCC1_ICE_CORE_CLK>;

		clock-names = "core", "iface", "ice_core";

		qcom,ice-clk-rates = <300000000 100000000>;

		interconnects = <&aggre1_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>,

			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDC_1>;