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Commit 28c4e264 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add support for performance lock on HOLI"

parents b3990d91 820ee338

bindings/cpufreq/cpufreq-qcom-hw.txt

+8 −0
Original line number Original line Diff line number Diff line
@@ -42,6 +42,14 @@ Properties: 
	Definition:	Indicate to check for Enable of FW before registering

	Definition:	Indicate to check for Enable of FW before registering

			with cpufreq.

			with cpufreq.





- qcom,perf-lock-support

	Usage:		Optional

	Value type:	bool

	Definition:	Indicate to check for performance lock support in FW.

			In case this property is present, the reg & reg-names

			should have the "pdmem-domainX" to indicate the

			corresponding bases.



* Property qcom,freq-domain

* Property qcom,freq-domain

Devices supporting freq-domain must set their "qcom,freq-domain" property with

Devices supporting freq-domain must set their "qcom,freq-domain" property with

phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.

phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.

qcom/holi.dtsi

+5 −2
Original line number Original line Diff line number Diff line
@@ -1227,13 +1227,16 @@ 




	cpufreq_hw: qcom,cpufreq-hw {

	cpufreq_hw: qcom,cpufreq-hw {

		compatible = "qcom,cpufreq-hw-epss";

		compatible = "qcom,cpufreq-hw-epss";

		reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>;

		reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>,

		reg-names = "freq-domain0", "freq-domain1";

			<0x0fd04504 0x4>, <0x0fd04508 0x4>;

		reg-names = "freq-domain0", "freq-domain1",

			"pdmem-domain0", "pdmem-domain1";

		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;

		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;

		clock-names = "xo", "alternate";

		clock-names = "xo", "alternate";

		qcom,lut-row-size = <4>;

		qcom,lut-row-size = <4>;

		qcom,max-lut-entries = <12>;

		qcom,max-lut-entries = <12>;

		qcom,skip-enable-check;

		qcom,skip-enable-check;

		qcom,perf-lock-support;

		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

				<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "dcvsh0_int", "dcvsh1_int";

		interrupt-names = "dcvsh0_int", "dcvsh1_int";