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Commit 820ee338 authored by Taniya Das's avatar Taniya Das
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ARM: dts: msm: Add support for performance lock on HOLI 

The cpufreq-hw requires the performance lock registers to be updated in
the cases where the SW DCVS is requested.

Change-Id: I6ac45a577904171a051c84b983363d9a2ea1164d
parent 7a315b16

qcom/holi.dtsi

+5 −2
Original line number Diff line number Diff line
@@ -1227,13 +1227,16 @@ 


	cpufreq_hw: qcom,cpufreq-hw {

		compatible = "qcom,cpufreq-hw-epss";

		reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>;

		reg-names = "freq-domain0", "freq-domain1";

		reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>,

			<0x0fd04504 0x4>, <0x0fd04508 0x4>;

		reg-names = "freq-domain0", "freq-domain1",

			"pdmem-domain0", "pdmem-domain1";

		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;

		clock-names = "xo", "alternate";

		qcom,lut-row-size = <4>;

		qcom,max-lut-entries = <12>;

		qcom,skip-enable-check;

		qcom,perf-lock-support;

		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "dcvsh0_int", "dcvsh1_int";