Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 64b7f9ac authored by Valentine Barshak's avatar Valentine Barshak Committed by Simon Horman
Browse files

ARM: shmobile: r8a7790: Add SATA clocks 



This adds SATA[01] clock support to R8A7790 SoC.

Signed-off-by: default avatarValentine Barshak <valentine.barshak@cogentembedded.com>
[horms+renesas@verge.net.au: resolved trivial conflicts]
Acked-by: default avatarMagnus Damm <damm@opensource.se>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent b89dfdfa

arch/arm/mach-shmobile/clock-r8a7790.c

+5 −0
Original line number Diff line number Diff line
@@ -196,6 +196,7 @@ enum { 
	MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,

	MSTP931, MSTP930, MSTP929, MSTP928,

	MSTP917,

	MSTP815, MSTP814,

	MSTP813,

	MSTP811, MSTP810, MSTP809, MSTP808,

	MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
@@ -226,6 +227,8 @@ static struct clk mstp_clks[MSTP_NR] = { 
	[MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */

	[MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */

	[MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */

	[MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */

	[MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */

	[MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */

	[MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */

	[MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
@@ -340,6 +343,8 @@ static struct clk_lookup lookups[] = { 
	CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),

	CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),

	CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),

	CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),

	CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),



	/* ICK */

	CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),