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Commit 62d212bd authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Maxime Ripard
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clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs



The PLLs on H3 have a lock bit, which will only be set to 1 when the PLL
is really working.

Add CLK_SET_RATE_UNGATE to the PLLs, otherwise it will timeout when
trying to set PLL clock frequency without enabling it.

Fixes: 0577e485 ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 2bd6bf03
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