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Commit 606afd50 authored by Yashwanth's avatar Yashwanth
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ARM: dts: msm: enable qsync along with VRR in shima target

This change enables qsync support for shima target along
with exisiting VRR. The required concurrency changes
are already included in the commit 30b1dd33 ("disp:
msm: sde: support qsync and vrr in same atomic commit").

Change-Id: I699334dc999857a8938bcb84d2ac4ca1386252c2
parent ef5bbdab
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