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Commit 5f41f919 authored by Marek Szyprowski's avatar Marek Szyprowski Committed by Russell King
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ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU cores 



Some big.LITTLE systems have I-Cache line size mismatch between
LITTLE and big cores. This patch adds a workaround for proper I-Cache
support on such systems. Without it, some class of the userspace code
(typically self-modifying) might suffer from random SIGILL failures.

Similar workaround already exists for ARM64 architecture. I has been
added by commit 116c81f4 ("arm64: Work around systems with mismatched
cache line sizes").

Signed-off-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
parent 304009a1

arch/arm/configs/exynos_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ CONFIG_MODULE_UNLOAD=y 
CONFIG_PARTITION_ADVANCED=y

CONFIG_ARCH_EXYNOS=y

CONFIG_ARCH_EXYNOS3=y

CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND=y

CONFIG_SMP=y

CONFIG_BIG_LITTLE=y

CONFIG_NR_CPUS=8

arch/arm/include/asm/cacheflush.h

+7 −0
Original line number Diff line number Diff line
@@ -479,4 +479,11 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size) 
void flush_uprobe_xol_access(struct page *page, unsigned long uaddr,

			     void *kaddr, unsigned long len);





#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND

void check_cpu_icache_size(int cpuid);

#else

static inline void check_cpu_icache_size(int cpuid) { }

#endif



#endif

arch/arm/kernel/smp.c

+1 −0
Original line number Diff line number Diff line
@@ -375,6 +375,7 @@ static void smp_store_cpu_info(unsigned int cpuid) 
	cpu_info->cpuid = read_cpuid_id();



	store_cpu_topology(cpuid);

	check_cpu_icache_size(cpuid);

}



/*

arch/arm/mm/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -780,6 +780,14 @@ config CPU_ICACHE_DISABLE 
	  Say Y here to disable the processor instruction cache. Unless

	  you have a reason not to or are unsure, say N.



config CPU_ICACHE_MISMATCH_WORKAROUND

	bool "Workaround for I-Cache line size mismatch between CPU cores"

	depends on SMP && CPU_V7

	help

	  Some big.LITTLE systems have I-Cache line size mismatch between

	  LITTLE and big cores.  Say Y here to enable a workaround for

	  proper I-Cache support on such systems.  If unsure, say N.



config CPU_DCACHE_DISABLE

	bool "Disable D-Cache (C-bit)"

	depends on (CPU_CP15 && !SMP) || CPU_V7M

arch/arm/mm/cache-v7.S

+13 −0
Original line number Diff line number Diff line
@@ -19,6 +19,14 @@ 


#include "proc-macros.S"



#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND

.globl icache_size

	.data

	.align	2

icache_size:

	.long	64

	.text

#endif

/*

 * The secondary kernel init calls v7_flush_dcache_all before it enables

 * the L1; however, the L1 comes out of reset in an undefined state, so
@@ -284,7 +292,12 @@ ENTRY(v7_coherent_user_range) 
	cmp	r12, r1

	blo	1b

	dsb	ishst

#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND

	ldr	r3, =icache_size

	ldr	r2, [r3, #0]

#else

	icache_line_size r2, r3

#endif

	sub	r3, r2, #1

	bic	r12, r0, r3

2: