Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 116c81f4 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Will Deacon
Browse files

arm64: Work around systems with mismatched cache line sizes 



Systems with differing CPU i-cache/d-cache line sizes can cause
problems with the cache management by software when the execution
is migrated from one to another. Usually, the application reads
the cache size on a CPU and then uses that length to perform cache
operations. However, if it gets migrated to another CPU with a smaller
cache line size, things could go completely wrong. To prevent such
cases, always use the smallest cache line size among the CPUs. The
kernel CPU feature infrastructure already keeps track of the safe
value for all CPUID registers including CTR. This patch works around
the problem by :

For kernel, dynamically patch the kernel to read the cache size
from the system wide copy of CTR_EL0.

For applications, trap read accesses to CTR_EL0 (by clearing the SCTLR.UCT)
and emulate the mrs instruction to return the system wide safe value
of CTR_EL0.

For faster access (i.e, avoiding to lookup the system wide value of CTR_EL0
via read_system_reg), we keep track of the pointer to table entry for
CTR_EL0 in the CPU feature infrastructure.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 9dbd5bb2

arch/arm64/include/asm/assembler.h

+22 −2
Original line number Diff line number Diff line
@@ -216,6 +216,20 @@ lr .req x30 // link register 
	.macro	mmid, rd, rn

	ldr	\rd, [\rn, #MM_CONTEXT_ID]

	.endm

/*

 * read_ctr - read CTR_EL0. If the system has mismatched

 * cache line sizes, provide the system wide safe value

 * from arm64_ftr_reg_ctrel0.sys_val

 */

	.macro	read_ctr, reg

alternative_if_not ARM64_MISMATCHED_CACHE_LINE_SIZE

	mrs	\reg, ctr_el0			// read CTR

	nop

alternative_else

	ldr_l	\reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL

alternative_endif

	.endm





/*

 * raw_dcache_line_size - get the minimum D-cache line size on this CPU
@@ -232,7 +246,10 @@ lr .req x30 // link register 
 * dcache_line_size - get the safe D-cache line size across all CPUs

 */

	.macro	dcache_line_size, reg, tmp

	raw_dcache_line_size	\reg, \tmp

	read_ctr	\tmp

	ubfm		\tmp, \tmp, #16, #19	// cache line size encoding

	mov		\reg, #4		// bytes per word

	lsl		\reg, \reg, \tmp	// actual cache line size

	.endm



/*
@@ -250,7 +267,10 @@ lr .req x30 // link register 
 * icache_line_size - get the safe I-cache line size across all CPUs

 */

	.macro	icache_line_size, reg, tmp

	raw_icache_line_size	\reg, \tmp

	read_ctr	\tmp

	and		\tmp, \tmp, #0xf	// cache line size encoding

	mov		\reg, #4		// bytes per word

	lsl		\reg, \reg, \tmp	// actual cache line size

	.endm



/*

arch/arm64/include/asm/cpufeature.h

+2 −1
Original line number Diff line number Diff line
@@ -39,8 +39,9 @@ 
#define ARM64_WORKAROUND_CAVIUM_27456		12

#define ARM64_HAS_32BIT_EL0			13

#define ARM64_HYP_OFFSET_LOW			14

#define ARM64_MISMATCHED_CACHE_LINE_SIZE	15



#define ARM64_NCAPS				15

#define ARM64_NCAPS				16



#ifndef __ASSEMBLY__

arch/arm64/include/asm/esr.h

+8 −0
Original line number Diff line number Diff line
@@ -149,6 +149,9 @@ 
					 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \

					 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \

					 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))



#define ESR_ELx_SYS64_ISS_SYS_OP_MASK	(ESR_ELx_SYS64_ISS_SYS_MASK | \

					 ESR_ELx_SYS64_ISS_DIR_MASK)

/*

 * User space cache operations have the following sysreg encoding

 * in System instructions.
@@ -167,6 +170,11 @@ 
#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \

				(ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \

				 ESR_ELx_SYS64_ISS_DIR_WRITE)



#define ESR_ELx_SYS64_ISS_SYS_CTR	ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)

#define ESR_ELx_SYS64_ISS_SYS_CTR_READ	(ESR_ELx_SYS64_ISS_SYS_CTR | \

					 ESR_ELx_SYS64_ISS_DIR_READ)



#ifndef __ASSEMBLY__

#include <asm/types.h>

arch/arm64/include/asm/sysreg.h

+1 −0
Original line number Diff line number Diff line
@@ -100,6 +100,7 @@ 
/* SCTLR_EL1 specific flags. */

#define SCTLR_EL1_UCI		(1 << 26)

#define SCTLR_EL1_SPAN		(1 << 23)

#define SCTLR_EL1_UCT		(1 << 15)

#define SCTLR_EL1_SED		(1 << 8)

#define SCTLR_EL1_CP15BEN	(1 << 5)

arch/arm64/kernel/asm-offsets.c

+2 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#include <linux/dma-mapping.h>

#include <linux/kvm_host.h>

#include <linux/suspend.h>

#include <asm/cpufeature.h>

#include <asm/thread_info.h>

#include <asm/memory.h>

#include <asm/smp_plat.h>
@@ -145,5 +146,6 @@ int main(void) 
  DEFINE(HIBERN_PBE_ORIG,	offsetof(struct pbe, orig_address));

  DEFINE(HIBERN_PBE_ADDR,	offsetof(struct pbe, address));

  DEFINE(HIBERN_PBE_NEXT,	offsetof(struct pbe, next));

  DEFINE(ARM64_FTR_SYSVAL,	offsetof(struct arm64_ftr_reg, sys_val));

  return 0;

}