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Commit 5ce5f61b authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Chris Wilson
Browse files

drm/i915: Handle catastrophic error on engine reset



If cat error is set, we need to clear it by acking it. Further,
if it is set, we must not do a normal request for reset.

v2: avoid goto (Chris)
v3: comment, error format, direct assign (Chris)
Bspec: 12567
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190412165353.16432-1-mika.kuoppala@linux.intel.com
parent 019d2600
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+4 −2
Original line number Diff line number Diff line
@@ -2446,8 +2446,10 @@ enum i915_power_well_id {
#define RING_HWS_PGA(base)	_MMIO((base) + 0x80)
#define RING_HWS_PGA_GEN6(base)	_MMIO((base) + 0x2080)
#define RING_RESET_CTL(base)	_MMIO((base) + 0xd0)
#define   RESET_CTL_REQUEST_RESET  (1 << 0)
#define   RESET_CTL_READY_TO_RESET (1 << 1)
#define   RESET_CTL_CAT_ERROR	   REG_BIT(2)
#define   RESET_CTL_READY_TO_RESET REG_BIT(1)
#define   RESET_CTL_REQUEST_RESET  REG_BIT(0)

#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)

#define HSW_GTT_CACHE_EN	_MMIO(0x4024)
+11 −1
Original line number Diff line number Diff line
@@ -495,7 +495,17 @@ static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
	int ret;

	ack = intel_uncore_read_fw(uncore, reg);
	if (!(ack & RESET_CTL_READY_TO_RESET)) {
	if (ack & RESET_CTL_CAT_ERROR) {
		/*
		 * For catastrophic errors, ready-for-reset sequence
		 * needs to be bypassed: HAS#396813
		 */
		request = RESET_CTL_CAT_ERROR;
		mask = RESET_CTL_CAT_ERROR;

		/* Catastrophic errors need to be cleared by HW */
		ack = 0;
	} else if (!(ack & RESET_CTL_READY_TO_RESET)) {
		request = RESET_CTL_REQUEST_RESET;
		mask = RESET_CTL_READY_TO_RESET;
		ack = RESET_CTL_READY_TO_RESET;