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Commit 019d2600 authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Chris Wilson
Browse files

drm/i915: Shortcut readiness to reset check 



If the engine says it is ready for reset, it is ready
so avoid further dancing and proceed.

v2: reg (Chris)
v3: request, ack, mask from following patch (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190412165335.16347-1-mika.kuoppala@linux.intel.com
parent e5604e2f

drivers/gpu/drm/i915/i915_reset.c

+16 −10
Original line number Diff line number Diff line
@@ -490,20 +490,26 @@ static int gen11_reset_engines(struct drm_i915_private *i915, 
static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)

{

	struct intel_uncore *uncore = engine->uncore;

	const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);

	u32 request, mask, ack;

	int ret;



	intel_uncore_write_fw(uncore,

			      RING_RESET_CTL(engine->mmio_base),

			      _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));

	ack = intel_uncore_read_fw(uncore, reg);

	if (!(ack & RESET_CTL_READY_TO_RESET)) {

		request = RESET_CTL_REQUEST_RESET;

		mask = RESET_CTL_READY_TO_RESET;

		ack = RESET_CTL_READY_TO_RESET;

	} else {

		return 0;

	}



	ret = __intel_wait_for_register_fw(uncore,

					   RING_RESET_CTL(engine->mmio_base),

					   RESET_CTL_READY_TO_RESET,

					   RESET_CTL_READY_TO_RESET,

					   700, 0,

					   NULL);

	intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));

	ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,

					   700, 0, NULL);

	if (ret)

		DRM_ERROR("%s: reset request timeout\n", engine->name);

		DRM_ERROR("%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n",

			  engine->name, request,

			  intel_uncore_read_fw(uncore, reg));



	return ret;

}