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Commit 5619d4e9 authored by Venkat Chinta's avatar Venkat Chinta
Browse files

msm: camera: ife: Unmask top level bus write IRQ bit



During VFE reset we mask all bits apart from reset done. Since
the top level bus write IRQ bit is common to all output ports
it is set during the initialize hardware sequence. However since
initialize hardware is not invoked in start only case that follows
flush, we must set it again.

CRs-Fixed: 2590331
Change-Id: I73f09e552779bd65f472178c1025594be03025fb
Signed-off-by: default avatarVenkat Chinta <vchinta@codeaurora.org>
parent a018ba6c
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+41 −1
Original line number Diff line number Diff line
@@ -4005,6 +4005,36 @@ static int cam_ife_mgr_reset_vfe_hw(struct cam_ife_hw_mgr *hw_mgr,
	return 0;
}

static int cam_ife_mgr_unmask_bus_wr_irq(struct cam_ife_hw_mgr *hw_mgr,
	uint32_t hw_idx)
{
	uint32_t i = 0, dummy_args = 0;
	struct cam_hw_intf *vfe_hw_intf;

	if (!hw_mgr) {
		CAM_DBG(CAM_ISP, "Invalid arguments");
		return -EINVAL;
	}

	for (i = 0; i < CAM_VFE_HW_NUM_MAX; i++) {
		if (hw_idx != hw_mgr->ife_devices[i]->hw_idx)
			continue;

		CAM_DBG(CAM_ISP, "Unmask VFE:%d BUS_WR IRQ", hw_idx);

		vfe_hw_intf = hw_mgr->ife_devices[i];

		vfe_hw_intf->hw_ops.process_cmd(vfe_hw_intf->hw_priv,
			CAM_ISP_HW_CMD_UNMASK_BUS_WR_IRQ,
			&dummy_args,
			sizeof(dummy_args));

		break;
	}

	return 0;
}

static int cam_ife_mgr_restart_hw(void *start_hw_args)
{
	int                               rc = -1;
@@ -4124,8 +4154,18 @@ static int cam_ife_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args)

	cam_tasklet_start(ctx->common.tasklet_info);

	if (ctx->init_done && start_isp->start_only)
	if (ctx->init_done && start_isp->start_only) {
		/* Unmask BUS_WR bit in VFE top */
		for (i = 0; i < ctx->num_base; i++) {
			rc = cam_ife_mgr_unmask_bus_wr_irq(hw_mgr_priv,
				ctx->base[i].idx);
			if (rc)
				CAM_ERR(CAM_ISP,
					"Failed to unmask VFE:%d BUS_WR IRQ rc:%d",
					ctx->base[i].idx, rc);
		}
		goto start_only;
	}

	/* set current csid debug information to CSID HW */
	for (i = 0; i < CAM_IFE_CSID_HW_NUM_MAX; i++) {
+1 −0
Original line number Diff line number Diff line
@@ -115,6 +115,7 @@ enum cam_isp_hw_cmd_type {
	CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP,
	CAM_ISP_HW_CMD_DUMP_HW,
	CAM_ISP_HW_CMD_FE_TRIGGER_CMD,
	CAM_ISP_HW_CMD_UNMASK_BUS_WR_IRQ,
	CAM_ISP_HW_CMD_MAX,
};

+1 −0
Original line number Diff line number Diff line
@@ -608,6 +608,7 @@ int cam_vfe_process_cmd(void *hw_priv, uint32_t cmd_type,
	case CAM_ISP_HW_CMD_UBWC_UPDATE_V2:
	case CAM_ISP_HW_CMD_WM_CONFIG_UPDATE:
	case CAM_ISP_HW_CMD_GET_SECURE_MODE:
	case CAM_ISP_HW_CMD_UNMASK_BUS_WR_IRQ:
		rc = core_info->vfe_bus->hw_ops.process_cmd(
			core_info->vfe_bus->bus_priv, cmd_type, cmd_args,
			arg_size);
+2 −0
Original line number Diff line number Diff line
@@ -265,6 +265,7 @@ static struct cam_vfe_bus_ver2_hw_info vfe170_bus_hw_info = {
		.addr_sync_no_sync            = 0x00002084,
		.debug_status_cfg             = 0x0000226C,
		.debug_status_0               = 0x00002270,
		.top_irq_mask_0               = 0x0000005C,
	},
	.num_client = 20,
	.bus_client_reg = {
@@ -849,6 +850,7 @@ static struct cam_vfe_bus_ver2_hw_info vfe170_bus_hw_info = {
			.max_height    = -1,
		},
	},
	.top_irq_shift = 9,
};

struct cam_vfe_hw_info cam_vfe170_hw_info = {
+2 −0
Original line number Diff line number Diff line
@@ -331,6 +331,7 @@ static struct cam_vfe_bus_ver2_hw_info vfe175_bus_hw_info = {
		.addr_sync_no_sync            = 0x00002084,
		.debug_status_cfg             = 0x0000226C,
		.debug_status_0               = 0x00002270,
		.top_irq_mask_0               = 0x0000005C,
	},
	.num_client = 24,
	.bus_client_reg = {
@@ -1019,6 +1020,7 @@ static struct cam_vfe_bus_ver2_hw_info vfe175_bus_hw_info = {
			.max_height    = 1080,
		},
	},
	.top_irq_shift = 9,
};

struct cam_vfe_hw_info cam_vfe175_hw_info = {
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