Merge "msm: kgsl: Mark the scratch buffer as privileged" (53582a26) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/gpu/msm/adreno.c

+14 −1

Original line number	Diff line number	Diff line
		@@ -60,6 +60,19 @@ int adreno_wake_nice = -7;
		/* Number of milliseconds to stay active active after a wake on touch */
		unsigned int adreno_wake_timeout = 100;

		static u32 get_ucode_version(const u32 *data)
		{
		u32 version;

		version = data[1];

		if ((version & 0xf) != 0xa)
		return version;

		version &= ~0xfff;
		return version \| ((data[3] & 0xfff000) >> 12);
		}

		int adreno_get_firmware(struct adreno_device *adreno_dev,
		const char fwfile, struct adreno_firmware firmware)
		{
		@@ -86,7 +99,7 @@ int adreno_get_firmware(struct adreno_device *adreno_dev,
		if (!ret) {
		memcpy(firmware->memdesc->hostptr, &fw->data[4], fw->size - 4);
		firmware->size = (fw->size - 4) / sizeof(u32);
		firmware->version = ((u32 )&fw->data[4]);
		firmware->version = get_ucode_version((u32 *)fw->data);
		}

		release_firmware(fw);

+2 −4

Original line number	Diff line number	Diff line
		@@ -249,8 +249,7 @@ enum adreno_preempt_states {
		/**
		* struct adreno_preemption
		* @state: The current state of preemption
		* @counters: Memory descriptor for the memory where the GPU writes the
		* preemption counters on switch
		* @scratch: Per-target scratch memory for implementation specific functionality
		* @timer: A timer to make sure preemption doesn't stall
		* @work: A work struct for the preemption worker (for 5XX)
		* preempt_level: The level of preemption (for 6XX)
		@@ -260,7 +259,7 @@ enum adreno_preempt_states {
		*/
		struct adreno_preemption {
		atomic_t state;
		struct kgsl_memdesc *counters;
		struct kgsl_memdesc *scratch;
		struct timer_list timer;
		struct work_struct work;
		unsigned int preempt_level;
		@@ -269,7 +268,6 @@ struct adreno_preemption {
		unsigned int count;
		};


		struct adreno_busy_data {
		unsigned int gpu_busy;
		unsigned int bif_ram_cycles;

+7 −4

Original line number	Diff line number	Diff line
		@@ -1621,12 +1621,15 @@ static int a5xx_post_start(struct adreno_device *adreno_dev)
		*cmds++ = 0xF;
		}

		if (adreno_is_preemption_enabled(adreno_dev))
		if (adreno_is_preemption_enabled(adreno_dev)) {
		cmds += _preemption_init(adreno_dev, rb, cmds, NULL);

		rb->_wptr = rb->_wptr - (42 - (cmds - start));

		ret = adreno_ringbuffer_submit_spin_nosync(rb, NULL, 2000);
		} else {
		rb->_wptr = rb->_wptr - (42 - (cmds - start));
		ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
		}

		if (ret)
		adreno_spin_idle_debug(adreno_dev,
		"hw initialization failed to idle\n");

+1 −1

Original line number	Diff line number	Diff line
		@@ -102,7 +102,7 @@ void a5xx_crashdump_init(struct adreno_device *adreno_dev);

		void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on);

		#define A5XX_CP_RB_CNTL_DEFAULT (((ilog2(4) << 8) & 0x1F00) \| \
		#define A5XX_CP_RB_CNTL_DEFAULT ((1 << 27) \| ((ilog2(4) << 8) & 0x1F00) \| \
		(ilog2(KGSL_RB_DWORDS >> 1) & 0x3F))
		/* GPMU interrupt multiplexor */
		#define FW_INTR_INFO (0)

+4 −4

Original line number	Diff line number	Diff line
		@@ -530,17 +530,17 @@ int a5xx_preemption_init(struct adreno_device *adreno_dev)
		INIT_WORK(&preempt->work, _a5xx_preemption_worker);

		/* Allocate mem for storing preemption counters */
		if (IS_ERR_OR_NULL(preempt->counters))
		preempt->counters = kgsl_allocate_global(device,
		if (IS_ERR_OR_NULL(preempt->scratch))
		preempt->scratch = kgsl_allocate_global(device,
		adreno_dev->num_ringbuffers *
		A5XX_CP_CTXRECORD_PREEMPTION_COUNTER_SIZE, 0, 0,
		"preemption_counters");

		ret = PTR_ERR_OR_ZERO(preempt->counters);
		ret = PTR_ERR_OR_ZERO(preempt->scratch);
		if (ret)
		return ret;

		addr = preempt->counters->gpuaddr;
		addr = preempt->scratch->gpuaddr;

		/* Allocate mem for storing preemption switch record */
		FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {