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Commit bea2e01a authored by Akhil P Oommen's avatar Akhil P Oommen
Browse files

msm: kgsl: Mark the scratch buffer as privileged 



Mark the scratch buffer as privileged so that it can only be accessed by
GPU through the ringbuffer. To accomplish this, we need to:

1. Disable the shadow rptr feature.
2. Trigger RPTR update from GPU using a WHERE_AM_I packet.
3. Add support for the new ucode.

Change-Id: I9b388f55f53b69028b9bbb2306cb43fd1297c52f
Signed-off-by: default avatarAkhil P Oommen <akhilpo@codeaurora.org>
parent f919cbe3

drivers/gpu/msm/adreno.c

+14 −1
Original line number Diff line number Diff line
@@ -60,6 +60,19 @@ int adreno_wake_nice = -7; 
/* Number of milliseconds to stay active active after a wake on touch */

unsigned int adreno_wake_timeout = 100;



static u32 get_ucode_version(const u32 *data)

{

	u32 version;



	version = data[1];



	if ((version & 0xf) != 0xa)

		return version;



	version &= ~0xfff;

	return  version | ((data[3] & 0xfff000) >> 12);

}



int adreno_get_firmware(struct adreno_device *adreno_dev,

		const char *fwfile, struct adreno_firmware *firmware)

{
@@ -86,7 +99,7 @@ int adreno_get_firmware(struct adreno_device *adreno_dev, 
	if (!ret) {

		memcpy(firmware->memdesc->hostptr, &fw->data[4], fw->size - 4);

		firmware->size = (fw->size - 4) / sizeof(u32);

		firmware->version = *((u32 *)&fw->data[4]);

		firmware->version = get_ucode_version((u32 *)fw->data);

	}



	release_firmware(fw);

drivers/gpu/msm/adreno_a5xx.c

+7 −4
Original line number Diff line number Diff line
@@ -1621,12 +1621,15 @@ static int a5xx_post_start(struct adreno_device *adreno_dev) 
		*cmds++ = 0xF;

	}



	if (adreno_is_preemption_enabled(adreno_dev))

	if (adreno_is_preemption_enabled(adreno_dev)) {

		cmds += _preemption_init(adreno_dev, rb, cmds, NULL);



		rb->_wptr = rb->_wptr - (42 - (cmds - start));



		ret = adreno_ringbuffer_submit_spin_nosync(rb, NULL, 2000);

	} else {

		rb->_wptr = rb->_wptr - (42 - (cmds - start));

		ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);

	}



	if (ret)

		adreno_spin_idle_debug(adreno_dev,

				"hw initialization failed to idle\n");

drivers/gpu/msm/adreno_a5xx.h

+1 −1
Original line number Diff line number Diff line
@@ -102,7 +102,7 @@ void a5xx_crashdump_init(struct adreno_device *adreno_dev); 


void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on);



#define A5XX_CP_RB_CNTL_DEFAULT (((ilog2(4) << 8) & 0x1F00) | \

#define A5XX_CP_RB_CNTL_DEFAULT ((1 << 27) | ((ilog2(4) << 8) & 0x1F00) | \

		(ilog2(KGSL_RB_DWORDS >> 1) & 0x3F))

/* GPMU interrupt multiplexor */

#define FW_INTR_INFO			(0)

drivers/gpu/msm/adreno_a6xx.c

+4 −4
Original line number Diff line number Diff line
@@ -870,7 +870,7 @@ static int a6xx_post_start(struct adreno_device *adreno_dev) 


	rb->_wptr = rb->_wptr - (42 - (cmds - start));



	ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);

	ret = adreno_ringbuffer_submit_spin_nosync(rb, NULL, 2000);

	if (ret)

		adreno_spin_idle_debug(adreno_dev,

			"hw preemption initialization failed to idle\n");
@@ -883,6 +883,8 @@ int a6xx_rb_start(struct adreno_device *adreno_dev) 
	const struct adreno_a6xx_core *a6xx_core = to_a6xx_core(adreno_dev);

	struct adreno_firmware *fw = ADRENO_FW(adreno_dev, ADRENO_FW_SQE);

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	u32 cp_rb_cntl = A6XX_CP_RB_CNTL_DEFAULT |

		(ADRENO_FEATURE(adreno_dev, ADRENO_APRIV) ? 0 : (1 << 27));

	struct adreno_ringbuffer *rb;

	uint64_t addr;

	int ret, i;
@@ -911,8 +913,7 @@ int a6xx_rb_start(struct adreno_device *adreno_dev) 
	 * The size of the ringbuffer in the hardware is the log2

	 * representation of the size in quadwords (sizedwords / 2).

	 */

	kgsl_regwrite(device, A6XX_CP_RB_CNTL,

					A6XX_CP_RB_CNTL_DEFAULT);

	kgsl_regwrite(device, A6XX_CP_RB_CNTL, cp_rb_cntl);



	kgsl_regwrite(device, A6XX_CP_RB_BASE,

		lower_32_bits(rb->buffer_desc->gpuaddr));
@@ -2438,7 +2439,6 @@ int a6xx_probe_common(struct platform_device *pdev, 
		adreno_dev->perfctr_ifpc_lo =

			A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L;





	return adreno_device_probe(pdev, adreno_dev);

}

drivers/gpu/msm/adreno_a6xx_preempt.c

+3 −1
Original line number Diff line number Diff line
@@ -615,6 +615,8 @@ static int a6xx_preemption_ringbuffer_init(struct adreno_device *adreno_dev, 
	struct adreno_ringbuffer *rb)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	u32 cp_rb_cntl = A6XX_CP_RB_CNTL_DEFAULT |

		(ADRENO_FEATURE(adreno_dev, ADRENO_APRIV) ? 0 : (1 << 27));



	if (IS_ERR_OR_NULL(rb->preemption_desc))

		rb->preemption_desc = kgsl_allocate_global(device,
@@ -648,7 +650,7 @@ static int a6xx_preemption_ringbuffer_init(struct adreno_device *adreno_dev, 
	kgsl_sharedmem_writel(rb->preemption_desc,

		PREEMPT_RECORD(data), 0);

	kgsl_sharedmem_writel(rb->preemption_desc,

		PREEMPT_RECORD(cntl), A6XX_CP_RB_CNTL_DEFAULT);

		PREEMPT_RECORD(cntl), cp_rb_cntl);

	kgsl_sharedmem_writel(rb->preemption_desc,

		PREEMPT_RECORD(rptr), 0);

	kgsl_sharedmem_writel(rb->preemption_desc,