Loading shima-camera.dtsi +28 −28 Original line number Original line Diff line number Diff line Loading @@ -29,10 +29,10 @@ rgltr-min-voltage = <0 0 1200000 880000>; rgltr-min-voltage = <0 0 1200000 880000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-load-current = <0 0 54000 96400>; rgltr-load-current = <0 0 54000 96400>; clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY0_CLK>, <&camcc CAM_CC_CSIPHY0_CLK>, <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>; <&camcc CAM_CC_CSI0PHYTIMER_CLK>; clock-names = "cphy_rx_clk_src", clock-names = "cphy_rx_clk_src", "csiphy0_clk", "csiphy0_clk", "csi0phytimer_clk_src", "csi0phytimer_clk_src", Loading Loading @@ -63,10 +63,10 @@ rgltr-min-voltage = <0 0 1200000 880000>; rgltr-min-voltage = <0 0 1200000 880000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-load-current = <0 0 54000 96400>; rgltr-load-current = <0 0 54000 96400>; clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY1_CLK>, <&camcc CAM_CC_CSIPHY1_CLK>, <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>; <&camcc CAM_CC_CSI1PHYTIMER_CLK>; clock-names = "cphy_rx_clk_src", clock-names = "cphy_rx_clk_src", "csiphy1_clk", "csiphy1_clk", "csi1phytimer_clk_src", "csi1phytimer_clk_src", Loading Loading @@ -97,10 +97,10 @@ rgltr-min-voltage = <0 0 1200000 880000>; rgltr-min-voltage = <0 0 1200000 880000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-load-current = <0 0 54000 96400>; rgltr-load-current = <0 0 54000 96400>; clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY2_CLK>, <&camcc CAM_CC_CSIPHY2_CLK>, <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>; <&camcc CAM_CC_CSI2PHYTIMER_CLK>; clock-names = "cphy_rx_clk_src", clock-names = "cphy_rx_clk_src", "csiphy2_clk", "csiphy2_clk", "csi2phytimer_clk_src", "csi2phytimer_clk_src", Loading Loading @@ -131,10 +131,10 @@ rgltr-min-voltage = <0 0 1200000 880000>; rgltr-min-voltage = <0 0 1200000 880000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-load-current = <0 0 54000 96400>; rgltr-load-current = <0 0 54000 96400>; clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY3_CLK>, <&camcc CAM_CC_CSIPHY3_CLK>, <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>; <&camcc CAM_CC_CSI3PHYTIMER_CLK>; clock-names = "cphy_rx_clk_src", clock-names = "cphy_rx_clk_src", "csiphy3_clk", "csiphy3_clk", "csi3phytimer_clk_src", "csi3phytimer_clk_src", Loading Loading @@ -165,10 +165,10 @@ rgltr-min-voltage = <0 0 1200000 880000>; rgltr-min-voltage = <0 0 1200000 880000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-load-current = <0 0 54000 96400>; rgltr-load-current = <0 0 54000 96400>; clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY4_CLK>, <&camcc CAM_CC_CSIPHY4_CLK>, <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK>; <&camcc CAM_CC_CSI4PHYTIMER_CLK>; clock-names = "cphy_rx_clk_src", clock-names = "cphy_rx_clk_src", "csiphy4_clk", "csiphy4_clk", "csi4phytimer_clk_src", "csi4phytimer_clk_src", Loading Loading @@ -199,10 +199,10 @@ rgltr-min-voltage = <0 0 1200000 880000>; rgltr-min-voltage = <0 0 1200000 880000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-load-current = <0 0 54000 96400>; rgltr-load-current = <0 0 54000 96400>; clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY5_CLK>, <&camcc CAM_CC_CSIPHY5_CLK>, <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, <&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK>; <&camcc CAM_CC_CSI5PHYTIMER_CLK>; clock-names = "cphy_rx_clk_src", clock-names = "cphy_rx_clk_src", "csiphy5_clk", "csiphy5_clk", "csi5phytimer_clk_src", "csi5phytimer_clk_src", Loading @@ -226,8 +226,8 @@ status = "ok"; status = "ok"; gdscr-supply = <&cam_cc_titan_top_gdsc>; gdscr-supply = <&cam_cc_titan_top_gdsc>; regulator-names = "gdscr"; regulator-names = "gdscr"; clocks = <&clock_camcc CAM_CC_CCI_0_CLK_SRC>, clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>, <&clock_camcc CAM_CC_CCI_0_CLK>; <&camcc CAM_CC_CCI_0_CLK>; clock-names = "cci_0_clk_src", clock-names = "cci_0_clk_src", "cci_0_clk"; "cci_0_clk"; src-clock-name = "cci_0_clk_src"; src-clock-name = "cci_0_clk_src"; Loading Loading @@ -319,8 +319,8 @@ status = "ok"; status = "ok"; gdscr-supply = <&cam_cc_titan_top_gdsc>; gdscr-supply = <&cam_cc_titan_top_gdsc>; regulator-names = "gdscr"; regulator-names = "gdscr"; clocks = <&clock_camcc CAM_CC_CCI_1_CLK_SRC>, clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>, <&clock_camcc CAM_CC_CCI_1_CLK>; <&camcc CAM_CC_CCI_1_CLK>; clock-names = "cci_1_clk_src", clock-names = "cci_1_clk_src", "cci_1_clk"; "cci_1_clk"; src-clock-name = "cci_1_clk_src"; src-clock-name = "cci_1_clk_src"; Loading Loading
shima-camera.dtsi +28 −28 Original line number Original line Diff line number Diff line Loading @@ -29,10 +29,10 @@ rgltr-min-voltage = <0 0 1200000 880000>; rgltr-min-voltage = <0 0 1200000 880000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-load-current = <0 0 54000 96400>; rgltr-load-current = <0 0 54000 96400>; clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY0_CLK>, <&camcc CAM_CC_CSIPHY0_CLK>, <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>; <&camcc CAM_CC_CSI0PHYTIMER_CLK>; clock-names = "cphy_rx_clk_src", clock-names = "cphy_rx_clk_src", "csiphy0_clk", "csiphy0_clk", "csi0phytimer_clk_src", "csi0phytimer_clk_src", Loading Loading @@ -63,10 +63,10 @@ rgltr-min-voltage = <0 0 1200000 880000>; rgltr-min-voltage = <0 0 1200000 880000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-load-current = <0 0 54000 96400>; rgltr-load-current = <0 0 54000 96400>; clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY1_CLK>, <&camcc CAM_CC_CSIPHY1_CLK>, <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>; <&camcc CAM_CC_CSI1PHYTIMER_CLK>; clock-names = "cphy_rx_clk_src", clock-names = "cphy_rx_clk_src", "csiphy1_clk", "csiphy1_clk", "csi1phytimer_clk_src", "csi1phytimer_clk_src", Loading Loading @@ -97,10 +97,10 @@ rgltr-min-voltage = <0 0 1200000 880000>; rgltr-min-voltage = <0 0 1200000 880000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-load-current = <0 0 54000 96400>; rgltr-load-current = <0 0 54000 96400>; clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY2_CLK>, <&camcc CAM_CC_CSIPHY2_CLK>, <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>; <&camcc CAM_CC_CSI2PHYTIMER_CLK>; clock-names = "cphy_rx_clk_src", clock-names = "cphy_rx_clk_src", "csiphy2_clk", "csiphy2_clk", "csi2phytimer_clk_src", "csi2phytimer_clk_src", Loading Loading @@ -131,10 +131,10 @@ rgltr-min-voltage = <0 0 1200000 880000>; rgltr-min-voltage = <0 0 1200000 880000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-load-current = <0 0 54000 96400>; rgltr-load-current = <0 0 54000 96400>; clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY3_CLK>, <&camcc CAM_CC_CSIPHY3_CLK>, <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>; <&camcc CAM_CC_CSI3PHYTIMER_CLK>; clock-names = "cphy_rx_clk_src", clock-names = "cphy_rx_clk_src", "csiphy3_clk", "csiphy3_clk", "csi3phytimer_clk_src", "csi3phytimer_clk_src", Loading Loading @@ -165,10 +165,10 @@ rgltr-min-voltage = <0 0 1200000 880000>; rgltr-min-voltage = <0 0 1200000 880000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-load-current = <0 0 54000 96400>; rgltr-load-current = <0 0 54000 96400>; clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY4_CLK>, <&camcc CAM_CC_CSIPHY4_CLK>, <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK>; <&camcc CAM_CC_CSI4PHYTIMER_CLK>; clock-names = "cphy_rx_clk_src", clock-names = "cphy_rx_clk_src", "csiphy4_clk", "csiphy4_clk", "csi4phytimer_clk_src", "csi4phytimer_clk_src", Loading Loading @@ -199,10 +199,10 @@ rgltr-min-voltage = <0 0 1200000 880000>; rgltr-min-voltage = <0 0 1200000 880000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-max-voltage = <0 0 1260000 1050000>; rgltr-load-current = <0 0 54000 96400>; rgltr-load-current = <0 0 54000 96400>; clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY5_CLK>, <&camcc CAM_CC_CSIPHY5_CLK>, <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, <&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK>; <&camcc CAM_CC_CSI5PHYTIMER_CLK>; clock-names = "cphy_rx_clk_src", clock-names = "cphy_rx_clk_src", "csiphy5_clk", "csiphy5_clk", "csi5phytimer_clk_src", "csi5phytimer_clk_src", Loading @@ -226,8 +226,8 @@ status = "ok"; status = "ok"; gdscr-supply = <&cam_cc_titan_top_gdsc>; gdscr-supply = <&cam_cc_titan_top_gdsc>; regulator-names = "gdscr"; regulator-names = "gdscr"; clocks = <&clock_camcc CAM_CC_CCI_0_CLK_SRC>, clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>, <&clock_camcc CAM_CC_CCI_0_CLK>; <&camcc CAM_CC_CCI_0_CLK>; clock-names = "cci_0_clk_src", clock-names = "cci_0_clk_src", "cci_0_clk"; "cci_0_clk"; src-clock-name = "cci_0_clk_src"; src-clock-name = "cci_0_clk_src"; Loading Loading @@ -319,8 +319,8 @@ status = "ok"; status = "ok"; gdscr-supply = <&cam_cc_titan_top_gdsc>; gdscr-supply = <&cam_cc_titan_top_gdsc>; regulator-names = "gdscr"; regulator-names = "gdscr"; clocks = <&clock_camcc CAM_CC_CCI_1_CLK_SRC>, clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>, <&clock_camcc CAM_CC_CCI_1_CLK>; <&camcc CAM_CC_CCI_1_CLK>; clock-names = "cci_1_clk_src", clock-names = "cci_1_clk_src", "cci_1_clk"; "cci_1_clk"; src-clock-name = "cci_1_clk_src"; src-clock-name = "cci_1_clk_src"; Loading