Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4c4fe169 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branch 'clk-mediatek' into clk-next 

* clk-mediatek:
  clk: mediatek: add clock support for MT7622 SoC
  clk: mediatek: add clocks dt-bindings required header for MT7622 SoC
  clk: mediatek: add the option for determining PLL source clock
  dt-bindings: clock: mediatek: document clk bindings for MediaTek MT7622 SoC
  clk: mediatek: mark mtk_infrasys_init_early __init
  clk: mediatek: Add MT2712 clock support
  clk: mediatek: Add dt-bindings for MT2712 clocks
  dt-bindings: ARM: Mediatek: Document bindings for MT2712
parents eed58151 2fc0a509

Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt

+2 −0
Original line number Original line Diff line number Diff line
@@ -7,7 +7,9 @@ Required Properties: 




- compatible: Should be one of:

- compatible: Should be one of:

	- "mediatek,mt2701-apmixedsys"

	- "mediatek,mt2701-apmixedsys"

	- "mediatek,mt2712-apmixedsys", "syscon"

	- "mediatek,mt6797-apmixedsys"

	- "mediatek,mt6797-apmixedsys"

	- "mediatek,mt7622-apmixedsys"

	- "mediatek,mt8135-apmixedsys"

	- "mediatek,mt8135-apmixedsys"

	- "mediatek,mt8173-apmixedsys"

	- "mediatek,mt8173-apmixedsys"

- #clock-cells: Must be 1

- #clock-cells: Must be 1

Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt

0 → 100644
+22 −0
Original line number Original line Diff line number Diff line 
MediaTek AUDSYS controller

============================



The MediaTek AUDSYS controller provides various clocks to the system.



Required Properties:



- compatible: Should be one of:

	- "mediatek,mt7622-audsys", "syscon"

- #clock-cells: Must be 1



The AUDSYS controller uses the common clk binding from

Documentation/devicetree/bindings/clock/clock-bindings.txt

The available clocks are defined in dt-bindings/clock/mt*-clk.h.



Example:



audsys: audsys@11220000 {

	compatible = "mediatek,mt7622-audsys", "syscon";

	reg = <0 0x11220000 0 0x1000>;

	#clock-cells = <1>;

};

Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt

+1 −0
Original line number Original line Diff line number Diff line
@@ -7,6 +7,7 @@ Required Properties: 




- compatible: Should be:

- compatible: Should be:

	- "mediatek,mt2701-bdpsys", "syscon"

	- "mediatek,mt2701-bdpsys", "syscon"

	- "mediatek,mt2712-bdpsys", "syscon"

- #clock-cells: Must be 1

- #clock-cells: Must be 1





The bdpsys controller uses the common clk binding from

The bdpsys controller uses the common clk binding from

Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt

+1 −0
Original line number Original line Diff line number Diff line
@@ -7,6 +7,7 @@ Required Properties: 




- compatible: Should be:

- compatible: Should be:

	- "mediatek,mt2701-ethsys", "syscon"

	- "mediatek,mt2701-ethsys", "syscon"

	- "mediatek,mt7622-ethsys", "syscon"

- #clock-cells: Must be 1

- #clock-cells: Must be 1





The ethsys controller uses the common clk binding from

The ethsys controller uses the common clk binding from

Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt

+1 −0
Original line number Original line Diff line number Diff line
@@ -8,6 +8,7 @@ Required Properties: 




- compatible: Should be:

- compatible: Should be:

	- "mediatek,mt2701-hifsys", "syscon"

	- "mediatek,mt2701-hifsys", "syscon"

	- "mediatek,mt7622-hifsys", "syscon"

- #clock-cells: Must be 1

- #clock-cells: Must be 1





The hifsys controller uses the common clk binding from

The hifsys controller uses the common clk binding from