clk: mediatek: add clock support for MT7622 SoC (2fc0a509) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/clk/mediatek/Kconfig

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		@@ -132,6 +132,36 @@ config COMMON_CLK_MT6797_VENCSYS
		---help---
		This driver supports Mediatek MT6797 vencsys clocks.

		config COMMON_CLK_MT7622
		bool "Clock driver for MediaTek MT7622"
		depends on ARCH_MEDIATEK \|\| COMPILE_TEST
		select COMMON_CLK_MEDIATEK
		default ARCH_MEDIATEK
		---help---
		This driver supports MediaTek MT7622 basic clocks and clocks
		required for various periperals found on MediaTek.

		config COMMON_CLK_MT7622_ETHSYS
		bool "Clock driver for MediaTek MT7622 ETHSYS"
		depends on COMMON_CLK_MT7622
		---help---
		This driver add support for clocks for Ethernet and SGMII
		required on MediaTek MT7622 SoC.

		config COMMON_CLK_MT7622_HIFSYS
		bool "Clock driver for MediaTek MT7622 HIFSYS"
		depends on COMMON_CLK_MT7622
		---help---
		This driver supports MediaTek MT7622 HIFSYS clocks providing
		to PCI-E and USB.

		config COMMON_CLK_MT7622_AUDSYS
		bool "Clock driver for MediaTek MT7622 AUDSYS"
		depends on COMMON_CLK_MT7622
		---help---
		This driver supports MediaTek MT7622 AUDSYS clocks providing
		to audio consumers such as I2S and TDM.

		config COMMON_CLK_MT8135
		bool "Clock driver for Mediatek MT8135"
		depends on (ARCH_MEDIATEK && ARM) \|\| COMPILE_TEST

drivers/clk/mediatek/Makefile

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		@@ -20,5 +20,9 @@ obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) += clk-mt2712-mfg.o
		obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) += clk-mt2712-mm.o
		obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) += clk-mt2712-vdec.o
		obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o
		obj-$(CONFIG_COMMON_CLK_MT7622) += clk-mt7622.o
		obj-$(CONFIG_COMMON_CLK_MT7622_ETHSYS) += clk-mt7622-eth.o
		obj-$(CONFIG_COMMON_CLK_MT7622_HIFSYS) += clk-mt7622-hif.o
		obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) += clk-mt7622-aud.o
		obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
		obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o

drivers/clk/mediatek/clk-mt7622-aud.c

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		/*
		* Copyright (c) 2017 MediaTek Inc.
		* Author: Chen Zhong <chen.zhong@mediatek.com>
		* Sean Wang <sean.wang@mediatek.com>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#include <linux/clk-provider.h>
		#include <linux/of.h>
		#include <linux/of_address.h>
		#include <linux/of_device.h>
		#include <linux/platform_device.h>

		#include "clk-mtk.h"
		#include "clk-gate.h"

		#include <dt-bindings/clock/mt7622-clk.h>

		#define GATE_AUDIO0(_id, _name, _parent, _shift) { \
		.id = _id, \
		.name = _name, \
		.parent_name = _parent, \
		.regs = &audio0_cg_regs, \
		.shift = _shift, \
		.ops = &mtk_clk_gate_ops_no_setclr, \
		}

		#define GATE_AUDIO1(_id, _name, _parent, _shift) { \
		.id = _id, \
		.name = _name, \
		.parent_name = _parent, \
		.regs = &audio1_cg_regs, \
		.shift = _shift, \
		.ops = &mtk_clk_gate_ops_no_setclr, \
		}

		#define GATE_AUDIO2(_id, _name, _parent, _shift) { \
		.id = _id, \
		.name = _name, \
		.parent_name = _parent, \
		.regs = &audio2_cg_regs, \
		.shift = _shift, \
		.ops = &mtk_clk_gate_ops_no_setclr, \
		}

		#define GATE_AUDIO3(_id, _name, _parent, _shift) { \
		.id = _id, \
		.name = _name, \
		.parent_name = _parent, \
		.regs = &audio3_cg_regs, \
		.shift = _shift, \
		.ops = &mtk_clk_gate_ops_no_setclr, \
		}

		static const struct mtk_gate_regs audio0_cg_regs = {
		.set_ofs = 0x0,
		.clr_ofs = 0x0,
		.sta_ofs = 0x0,
		};

		static const struct mtk_gate_regs audio1_cg_regs = {
		.set_ofs = 0x10,
		.clr_ofs = 0x10,
		.sta_ofs = 0x10,
		};

		static const struct mtk_gate_regs audio2_cg_regs = {
		.set_ofs = 0x14,
		.clr_ofs = 0x14,
		.sta_ofs = 0x14,
		};

		static const struct mtk_gate_regs audio3_cg_regs = {
		.set_ofs = 0x634,
		.clr_ofs = 0x634,
		.sta_ofs = 0x634,
		};

		static const struct mtk_gate audio_clks[] = {
		/* AUDIO0 */
		GATE_AUDIO0(CLK_AUDIO_AFE, "audio_afe", "rtc", 2),
		GATE_AUDIO0(CLK_AUDIO_HDMI, "audio_hdmi", "apll1_ck_sel", 20),
		GATE_AUDIO0(CLK_AUDIO_SPDF, "audio_spdf", "apll1_ck_sel", 21),
		GATE_AUDIO0(CLK_AUDIO_APLL, "audio_apll", "apll1_ck_sel", 23),
		/* AUDIO1 */
		GATE_AUDIO1(CLK_AUDIO_I2SIN1, "audio_i2sin1", "a1sys_hp_sel", 0),
		GATE_AUDIO1(CLK_AUDIO_I2SIN2, "audio_i2sin2", "a1sys_hp_sel", 1),
		GATE_AUDIO1(CLK_AUDIO_I2SIN3, "audio_i2sin3", "a1sys_hp_sel", 2),
		GATE_AUDIO1(CLK_AUDIO_I2SIN4, "audio_i2sin4", "a1sys_hp_sel", 3),
		GATE_AUDIO1(CLK_AUDIO_I2SO1, "audio_i2so1", "a1sys_hp_sel", 6),
		GATE_AUDIO1(CLK_AUDIO_I2SO2, "audio_i2so2", "a1sys_hp_sel", 7),
		GATE_AUDIO1(CLK_AUDIO_I2SO3, "audio_i2so3", "a1sys_hp_sel", 8),
		GATE_AUDIO1(CLK_AUDIO_I2SO4, "audio_i2so4", "a1sys_hp_sel", 9),
		GATE_AUDIO1(CLK_AUDIO_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
		GATE_AUDIO1(CLK_AUDIO_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
		GATE_AUDIO1(CLK_AUDIO_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
		GATE_AUDIO1(CLK_AUDIO_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
		GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20),
		GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21),
		GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22),
		/* AUDIO2 */
		GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0),
		GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1),
		GATE_AUDIO2(CLK_AUDIO_UL3, "audio_ul3", "a1sys_hp_sel", 2),
		GATE_AUDIO2(CLK_AUDIO_UL4, "audio_ul4", "a1sys_hp_sel", 3),
		GATE_AUDIO2(CLK_AUDIO_UL5, "audio_ul5", "a1sys_hp_sel", 4),
		GATE_AUDIO2(CLK_AUDIO_UL6, "audio_ul6", "a1sys_hp_sel", 5),
		GATE_AUDIO2(CLK_AUDIO_DL1, "audio_dl1", "a1sys_hp_sel", 6),
		GATE_AUDIO2(CLK_AUDIO_DL2, "audio_dl2", "a1sys_hp_sel", 7),
		GATE_AUDIO2(CLK_AUDIO_DL3, "audio_dl3", "a1sys_hp_sel", 8),
		GATE_AUDIO2(CLK_AUDIO_DL4, "audio_dl4", "a1sys_hp_sel", 9),
		GATE_AUDIO2(CLK_AUDIO_DL5, "audio_dl5", "a1sys_hp_sel", 10),
		GATE_AUDIO2(CLK_AUDIO_DL6, "audio_dl6", "a1sys_hp_sel", 11),
		GATE_AUDIO2(CLK_AUDIO_DLMCH, "audio_dlmch", "a1sys_hp_sel", 12),
		GATE_AUDIO2(CLK_AUDIO_ARB1, "audio_arb1", "a1sys_hp_sel", 13),
		GATE_AUDIO2(CLK_AUDIO_AWB, "audio_awb", "a1sys_hp_sel", 14),
		GATE_AUDIO2(CLK_AUDIO_AWB2, "audio_awb2", "a1sys_hp_sel", 15),
		GATE_AUDIO2(CLK_AUDIO_DAI, "audio_dai", "a1sys_hp_sel", 16),
		GATE_AUDIO2(CLK_AUDIO_MOD, "audio_mod", "a1sys_hp_sel", 17),
		/* AUDIO3 */
		GATE_AUDIO3(CLK_AUDIO_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
		GATE_AUDIO3(CLK_AUDIO_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
		GATE_AUDIO3(CLK_AUDIO_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
		GATE_AUDIO3(CLK_AUDIO_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
		GATE_AUDIO3(CLK_AUDIO_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
		GATE_AUDIO3(CLK_AUDIO_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
		GATE_AUDIO3(CLK_AUDIO_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
		GATE_AUDIO3(CLK_AUDIO_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
		GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
		};

		static int clk_mt7622_audiosys_init(struct platform_device *pdev)
		{
		struct clk_onecell_data *clk_data;
		struct device_node *node = pdev->dev.of_node;
		int r;

		clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);

		mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
		clk_data);

		r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
		if (r)
		dev_err(&pdev->dev,
		"could not register clock provider: %s: %d\n",
		pdev->name, r);

		return r;
		}

		static const struct of_device_id of_match_clk_mt7622_aud[] = {
		{
		.compatible = "mediatek,mt7622-audsys",
		.data = clk_mt7622_audiosys_init,
		}, {
		/* sentinel */
		}
		};

		static int clk_mt7622_aud_probe(struct platform_device *pdev)
		{
		int (clk_init)(struct platform_device );
		int r;

		clk_init = of_device_get_match_data(&pdev->dev);
		if (!clk_init)
		return -EINVAL;

		r = clk_init(pdev);
		if (r)
		dev_err(&pdev->dev,
		"could not register clock provider: %s: %d\n",
		pdev->name, r);

		return r;
		}

		static struct platform_driver clk_mt7622_aud_drv = {
		.probe = clk_mt7622_aud_probe,
		.driver = {
		.name = "clk-mt7622-aud",
		.of_match_table = of_match_clk_mt7622_aud,
		},
		};

		builtin_platform_driver(clk_mt7622_aud_drv);

drivers/clk/mediatek/clk-mt7622-eth.c

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		/*
		* Copyright (c) 2017 MediaTek Inc.
		* Author: Chen Zhong <chen.zhong@mediatek.com>
		* Sean Wang <sean.wang@mediatek.com>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#include <linux/clk-provider.h>
		#include <linux/of.h>
		#include <linux/of_address.h>
		#include <linux/of_device.h>
		#include <linux/platform_device.h>

		#include "clk-mtk.h"
		#include "clk-gate.h"

		#include <dt-bindings/clock/mt7622-clk.h>

		#define GATE_ETH(_id, _name, _parent, _shift) { \
		.id = _id, \
		.name = _name, \
		.parent_name = _parent, \
		.regs = &eth_cg_regs, \
		.shift = _shift, \
		.ops = &mtk_clk_gate_ops_no_setclr_inv, \
		}

		static const struct mtk_gate_regs eth_cg_regs = {
		.set_ofs = 0x30,
		.clr_ofs = 0x30,
		.sta_ofs = 0x30,
		};

		static const struct mtk_gate eth_clks[] = {
		GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5),
		GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6),
		GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
		GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
		GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
		};

		static const struct mtk_gate_regs sgmii_cg_regs = {
		.set_ofs = 0xE4,
		.clr_ofs = 0xE4,
		.sta_ofs = 0xE4,
		};

		#define GATE_SGMII(_id, _name, _parent, _shift) { \
		.id = _id, \
		.name = _name, \
		.parent_name = _parent, \
		.regs = &sgmii_cg_regs, \
		.shift = _shift, \
		.ops = &mtk_clk_gate_ops_no_setclr_inv, \
		}

		static const struct mtk_gate sgmii_clks[] = {
		GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en",
		"ssusb_tx250m", 2),
		GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en",
		"ssusb_eq_rx250m", 3),
		GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
		"ssusb_cdr_ref", 4),
		GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
		"ssusb_cdr_fb", 5),
		};

		static int clk_mt7622_ethsys_init(struct platform_device *pdev)
		{
		struct clk_onecell_data *clk_data;
		struct device_node *node = pdev->dev.of_node;
		int r;

		clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);

		mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
		clk_data);

		r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
		if (r)
		dev_err(&pdev->dev,
		"could not register clock provider: %s: %d\n",
		pdev->name, r);

		mtk_register_reset_controller(node, 1, 0x34);

		return r;
		}

		static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
		{
		struct clk_onecell_data *clk_data;
		struct device_node *node = pdev->dev.of_node;
		int r;

		clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);

		mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
		clk_data);

		r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
		if (r)
		dev_err(&pdev->dev,
		"could not register clock provider: %s: %d\n",
		pdev->name, r);

		return r;
		}

		static const struct of_device_id of_match_clk_mt7622_eth[] = {
		{
		.compatible = "mediatek,mt7622-ethsys",
		.data = clk_mt7622_ethsys_init,
		}, {
		.compatible = "mediatek,mt7622-sgmiisys",
		.data = clk_mt7622_sgmiisys_init,
		}, {
		/* sentinel */
		}
		};

		static int clk_mt7622_eth_probe(struct platform_device *pdev)
		{
		int (clk_init)(struct platform_device );
		int r;

		clk_init = of_device_get_match_data(&pdev->dev);
		if (!clk_init)
		return -EINVAL;

		r = clk_init(pdev);
		if (r)
		dev_err(&pdev->dev,
		"could not register clock provider: %s: %d\n",
		pdev->name, r);

		return r;
		}

		static struct platform_driver clk_mt7622_eth_drv = {
		.probe = clk_mt7622_eth_probe,
		.driver = {
		.name = "clk-mt7622-eth",
		.of_match_table = of_match_clk_mt7622_eth,
		},
		};

		builtin_platform_driver(clk_mt7622_eth_drv);

drivers/clk/mediatek/clk-mt7622-hif.c

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		/*
		* Copyright (c) 2017 MediaTek Inc.
		* Author: Chen Zhong <chen.zhong@mediatek.com>
		* Sean Wang <sean.wang@mediatek.com>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#include <linux/clk-provider.h>
		#include <linux/of.h>
		#include <linux/of_address.h>
		#include <linux/of_device.h>
		#include <linux/platform_device.h>

		#include "clk-mtk.h"
		#include "clk-gate.h"

		#include <dt-bindings/clock/mt7622-clk.h>

		#define GATE_PCIE(_id, _name, _parent, _shift) { \
		.id = _id, \
		.name = _name, \
		.parent_name = _parent, \
		.regs = &pcie_cg_regs, \
		.shift = _shift, \
		.ops = &mtk_clk_gate_ops_no_setclr_inv, \
		}

		#define GATE_SSUSB(_id, _name, _parent, _shift) { \
		.id = _id, \
		.name = _name, \
		.parent_name = _parent, \
		.regs = &ssusb_cg_regs, \
		.shift = _shift, \
		.ops = &mtk_clk_gate_ops_no_setclr_inv, \
		}

		static const struct mtk_gate_regs pcie_cg_regs = {
		.set_ofs = 0x30,
		.clr_ofs = 0x30,
		.sta_ofs = 0x30,
		};

		static const struct mtk_gate_regs ssusb_cg_regs = {
		.set_ofs = 0x30,
		.clr_ofs = 0x30,
		.sta_ofs = 0x30,
		};

		static const struct mtk_gate ssusb_clks[] = {
		GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
		"to_u2_phy_1p", 0),
		GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
		GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
		GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
		GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "axi_sel", 7),
		GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "hif_sel", 8),
		};

		static const struct mtk_gate pcie_clks[] = {
		GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
		GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
		GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "axi_sel", 14),
		GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "hif_sel", 15),
		GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
		GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
		GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
		GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
		GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "axi_sel", 20),
		GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "hif_sel", 21),
		GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
		GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
		GATE_PCIE(CLK_SATA_AHB_EN, "sata_ahb_en", "axi_sel", 26),
		GATE_PCIE(CLK_SATA_AXI_EN, "sata_axi_en", "hif_sel", 27),
		GATE_PCIE(CLK_SATA_ASIC_EN, "sata_asic_en", "sata_asic", 28),
		GATE_PCIE(CLK_SATA_RBC_EN, "sata_rbc_en", "sata_rbc", 29),
		GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
		};

		static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
		{
		struct clk_onecell_data *clk_data;
		struct device_node *node = pdev->dev.of_node;
		int r;

		clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);

		mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
		clk_data);

		r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
		if (r)
		dev_err(&pdev->dev,
		"could not register clock provider: %s: %d\n",
		pdev->name, r);

		mtk_register_reset_controller(node, 1, 0x34);

		return r;
		}

		static int clk_mt7622_pciesys_init(struct platform_device *pdev)
		{
		struct clk_onecell_data *clk_data;
		struct device_node *node = pdev->dev.of_node;
		int r;

		clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);

		mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
		clk_data);

		r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
		if (r)
		dev_err(&pdev->dev,
		"could not register clock provider: %s: %d\n",
		pdev->name, r);

		mtk_register_reset_controller(node, 1, 0x34);

		return r;
		}

		static const struct of_device_id of_match_clk_mt7622_hif[] = {
		{
		.compatible = "mediatek,mt7622-pciesys",
		.data = clk_mt7622_pciesys_init,
		}, {
		.compatible = "mediatek,mt7622-ssusbsys",
		.data = clk_mt7622_ssusbsys_init,
		}, {
		/* sentinel */
		}
		};

		static int clk_mt7622_hif_probe(struct platform_device *pdev)
		{
		int (clk_init)(struct platform_device );
		int r;

		clk_init = of_device_get_match_data(&pdev->dev);
		if (!clk_init)
		return -EINVAL;

		r = clk_init(pdev);
		if (r)
		dev_err(&pdev->dev,
		"could not register clock provider: %s: %d\n",
		pdev->name, r);

		return r;
		}

		static struct platform_driver clk_mt7622_hif_drv = {
		.probe = clk_mt7622_hif_probe,
		.driver = {
		.name = "clk-mt7622-hif",
		.of_match_table = of_match_clk_mt7622_hif,
		},
		};

		builtin_platform_driver(clk_mt7622_hif_drv);