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Commit 4bdafb9d authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Remove i915.enable_ppgtt override 



Now that we are confident in providing full-ppgtt where supported,
remove the ability to override the context isolation.

v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted.
v3: s/USES/HAS/ to match usage and reject attempts to load the module on
old GVT-g setups that do not provide support for full-ppgtt.
v4: Insulate ABI ppGTT values from our internal enum (later plans
involve moving ppGTT depth out of the enum, thus potentially breaking
ABI unless we document the current values).

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Acked-by: default avatarZhi Wang <zhi.a.wang@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180926201222.5643-1-chris@chris-wilson.co.uk
parent c5f6d578

drivers/gpu/drm/i915/i915_drv.c

+10 −12
Original line number Diff line number Diff line
@@ -345,7 +345,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, 
		value = HAS_WT(dev_priv);

		break;

	case I915_PARAM_HAS_ALIASING_PPGTT:

		value = USES_PPGTT(dev_priv);

		value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);

		break;

	case I915_PARAM_HAS_SEMAPHORES:

		value = HAS_LEGACY_SEMAPHORES(dev_priv);
@@ -1049,17 +1049,6 @@ static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv) 


static void intel_sanitize_options(struct drm_i915_private *dev_priv)

{

	/*

	 * i915.enable_ppgtt is read-only, so do an early pass to validate the

	 * user's requested state against the hardware/driver capabilities.  We

	 * do this now so that we can print out any log messages once rather

	 * than every time we check intel_enable_ppgtt().

	 */

	i915_modparams.enable_ppgtt =

		intel_sanitize_enable_ppgtt(dev_priv,

					    i915_modparams.enable_ppgtt);

	DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);



	intel_gvt_sanitize_options(dev_priv);

}
@@ -1374,6 +1363,15 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) 


	intel_device_info_runtime_init(mkwrite_device_info(dev_priv));



	if (HAS_PPGTT(dev_priv)) {

		if (intel_vgpu_active(dev_priv) &&

		    !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {

			i915_report_error(dev_priv,

					  "incompatible vGPU found, support for isolated ppGTT required\n");

			return -ENXIO;

		}

	}



	intel_sanitize_options(dev_priv);



	i915_perf_init(dev_priv);

drivers/gpu/drm/i915/i915_drv.h

+8 −6
Original line number Diff line number Diff line
@@ -2597,9 +2597,14 @@ intel_info(const struct drm_i915_private *dev_priv) 


#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)



#define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)

#define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)

#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)

#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)

#define HAS_PPGTT(dev_priv) \

	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)

#define HAS_FULL_PPGTT(dev_priv) \

	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)

#define HAS_FULL_48BIT_PPGTT(dev_priv)	\

	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)



#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \

	GEM_BUG_ON((sizes) == 0); \

	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
@@ -2747,9 +2752,6 @@ intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) 
	return IS_BROXTON(dev_priv) && intel_vtd_active();

}



int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,

				int enable_ppgtt);



/* i915_drv.c */

void __printf(3, 4)

__i915_printk(struct drm_i915_private *dev_priv, const char *level,

drivers/gpu/drm/i915/i915_gem_context.c

+1 −1
Original line number Diff line number Diff line
@@ -414,7 +414,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv, 
	if (IS_ERR(ctx))

		return ctx;



	if (USES_FULL_PPGTT(dev_priv)) {

	if (HAS_FULL_PPGTT(dev_priv)) {

		struct i915_hw_ppgtt *ppgtt;



		ppgtt = i915_ppgtt_create(dev_priv, file_priv);

drivers/gpu/drm/i915/i915_gem_gtt.c

+7 −81
Original line number Diff line number Diff line
@@ -133,55 +133,6 @@ static inline void i915_ggtt_invalidate(struct drm_i915_private *i915) 
	i915->ggtt.invalidate(i915);

}



int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,

			       	int enable_ppgtt)

{

	bool has_full_ppgtt;

	bool has_full_48bit_ppgtt;



	if (!dev_priv->info.has_aliasing_ppgtt)

		return 0;



	has_full_ppgtt = dev_priv->info.has_full_ppgtt;

	has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;



	if (intel_vgpu_active(dev_priv)) {

		/* GVT-g has no support for 32bit ppgtt */

		has_full_ppgtt = false;

		has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);

	}



	/*

	 * We don't allow disabling PPGTT for gen8+ as it's a requirement for

	 * execlists, the sole mechanism available to submit work.

	 */

	if (enable_ppgtt == 0 && !HAS_EXECLISTS(dev_priv))

		return 0;



	if (enable_ppgtt == 1)

		return 1;



	if (enable_ppgtt == 2 && has_full_ppgtt)

		return 2;



	if (enable_ppgtt == 3 && has_full_48bit_ppgtt)

		return 3;



	/* Disable ppgtt on SNB if VT-d is on. */

	if (IS_GEN6(dev_priv) && intel_vtd_active()) {

		DRM_INFO("Disabling PPGTT because VT-d is on\n");

		return 0;

	}



	if (has_full_48bit_ppgtt)

		return 3;



	if (has_full_ppgtt)

		return 2;



	return 1;

}



static int ppgtt_bind_vma(struct i915_vma *vma,

			  enum i915_cache_level cache_level,

			  u32 unused)
@@ -1647,7 +1598,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915) 
	ppgtt->vm.i915 = i915;

	ppgtt->vm.dma = &i915->drm.pdev->dev;



	ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?

	ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?

		1ULL << 48 :

		1ULL << 32;
@@ -1782,19 +1733,6 @@ static inline void gen6_write_pde(const struct gen6_hw_ppgtt *ppgtt, 
		  ppgtt->pd_addr + pde);

}



static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)

{

	struct intel_engine_cs *engine;

	enum intel_engine_id id;



	for_each_engine(engine, dev_priv, id) {

		u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?

				 GEN8_GFX_PPGTT_48B : 0;

		I915_WRITE(RING_MODE_GEN7(engine),

			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));

	}

}



static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)

{

	struct intel_engine_cs *engine;
@@ -1834,6 +1772,7 @@ static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv) 
	ecochk = I915_READ(GAM_ECOCHK);

	I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);



	if (HAS_PPGTT(dev_priv)) /* may be disabled for VT-d */

		I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));

}
@@ -2237,23 +2176,10 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv) 
{

	gtt_write_workarounds(dev_priv);



	/* In the case of execlists, PPGTT is enabled by the context descriptor

	 * and the PDPs are contained within the context itself.  We don't

	 * need to do anything here. */

	if (HAS_LOGICAL_RING_CONTEXTS(dev_priv))

		return 0;



	if (!USES_PPGTT(dev_priv))

		return 0;



	if (IS_GEN6(dev_priv))

		gen6_ppgtt_enable(dev_priv);

	else if (IS_GEN7(dev_priv))

		gen7_ppgtt_enable(dev_priv);

	else if (INTEL_GEN(dev_priv) >= 8)

		gen8_ppgtt_enable(dev_priv);

	else

		MISSING_CASE(INTEL_GEN(dev_priv));



	return 0;

}
@@ -2952,7 +2878,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) 
	/* And finally clear the reserved guard page */

	ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);



	if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {

	if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {

		ret = i915_gem_init_aliasing_ppgtt(dev_priv);

		if (ret)

			goto err;
@@ -3275,7 +3201,7 @@ static void bdw_setup_private_ppat(struct intel_ppat *ppat) 
	ppat->match = bdw_private_pat_match;

	ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);



	if (!USES_PPGTT(ppat->i915)) {

	if (!HAS_PPGTT(ppat->i915)) {

		/* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,

		 * so RTL will always use the value corresponding to

		 * pat_sel = 000".
@@ -3402,7 +3328,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) 
	ggtt->vm.cleanup = gen6_gmch_remove;

	ggtt->vm.insert_page = gen8_ggtt_insert_page;

	ggtt->vm.clear_range = nop_clear_range;

	if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv))

	if (intel_scanout_needs_vtd_wa(dev_priv))

		ggtt->vm.clear_range = gen8_ggtt_clear_range;



	ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
@@ -3609,7 +3535,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) 
	/* Only VLV supports read-only GGTT mappings */

	ggtt->vm.has_read_only = IS_VALLEYVIEW(dev_priv);



	if (!HAS_LLC(dev_priv) && !USES_PPGTT(dev_priv))

	if (!HAS_LLC(dev_priv) && !HAS_PPGTT(dev_priv))

		ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;

	mutex_unlock(&dev_priv->drm.struct_mutex);

drivers/gpu/drm/i915/i915_gpu_error.c

+2 −2
Original line number Diff line number Diff line
@@ -474,7 +474,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m, 
			err_printf(m, "  SYNC_2: 0x%08x\n",

				   ee->semaphore_mboxes[2]);

	}

	if (USES_PPGTT(m->i915)) {

	if (HAS_PPGTT(m->i915)) {

		err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);



		if (INTEL_GEN(m->i915) >= 8) {
@@ -1230,7 +1230,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error, 
	ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,

						  engine);



	if (USES_PPGTT(dev_priv)) {

	if (HAS_PPGTT(dev_priv)) {

		int i;



		ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));