Merge remote-tracking branch 'asoc/topic/intel' into asoc-next (4a2447b4) · Commits · e / devices / android_kernel_fairphone_FP5

include/sound/hda_register.h

+36 −0

Original line number	Diff line number	Diff line
		@@ -89,6 +89,19 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
		#define AZX_REG_SD_BDLPL 0x18
		#define AZX_REG_SD_BDLPU 0x1c

		/* GTS registers */
		#define AZX_REG_LLCH 0x14

		#define AZX_REG_GTS_BASE 0x520

		#define AZX_REG_GTSCC (AZX_REG_GTS_BASE + 0x00)
		#define AZX_REG_WALFCC (AZX_REG_GTS_BASE + 0x04)
		#define AZX_REG_TSCCL (AZX_REG_GTS_BASE + 0x08)
		#define AZX_REG_TSCCU (AZX_REG_GTS_BASE + 0x0C)
		#define AZX_REG_LLPFOC (AZX_REG_GTS_BASE + 0x14)
		#define AZX_REG_LLPCL (AZX_REG_GTS_BASE + 0x18)
		#define AZX_REG_LLPCU (AZX_REG_GTS_BASE + 0x1C)

		/* Haswell/Broadwell display HD-A controller Extended Mode registers */
		#define AZX_REG_HSW_EM4 0x100c
		#define AZX_REG_HSW_EM5 0x1010
		@@ -242,6 +255,29 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
		/* Interval used to calculate the iterating register offset */
		#define AZX_DRSM_INTERVAL 0x08

		/* Global time synchronization registers */
		#define GTSCC_TSCCD_MASK 0x80000000
		#define GTSCC_TSCCD_SHIFT BIT(31)
		#define GTSCC_TSCCI_MASK 0x20
		#define GTSCC_CDMAS_DMA_DIR_SHIFT 4

		#define WALFCC_CIF_MASK 0x1FF
		#define WALFCC_FN_SHIFT 9
		#define HDA_CLK_CYCLES_PER_FRAME 512

		/*
		* An error occurs near frame "rollover". The clocks in frame value indicates
		* whether this error may have occurred. Here we use the value of 10. Please
		* see the errata for the right number [<10]
		*/
		#define HDA_MAX_CYCLE_VALUE 499
		#define HDA_MAX_CYCLE_OFFSET 10
		#define HDA_MAX_CYCLE_READ_RETRY 10

		#define TSCCU_CCU_SHIFT 32
		#define LLPC_CCU_SHIFT 32


		/*
		* helpers to read the stream position
		*/

include/sound/hdaudio.h

+13 −0

Original line number	Diff line number	Diff line
		@@ -245,6 +245,12 @@ struct hdac_rb {

		/*
		* HD-audio bus base driver
		*
		* @ppcap: pp capabilities pointer
		* @spbcap: SPIB capabilities pointer
		* @mlcap: MultiLink capabilities pointer
		* @gtscap: gts capabilities pointer
		* @drsmcap: dma resume capabilities pointer
		*/
		struct hdac_bus {
		struct device *dev;
		@@ -256,6 +262,12 @@ struct hdac_bus {
		void __iomem *remap_addr;
		int irq;

		void __iomem *ppcap;
		void __iomem *spbcap;
		void __iomem *mlcap;
		void __iomem *gtscap;
		void __iomem *drsmcap;

		/* codec linked list */
		struct list_head codec_list;
		unsigned int num_codecs;
		@@ -335,6 +347,7 @@ static inline void snd_hdac_codec_link_down(struct hdac_device *codec)
		int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val);
		int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
		unsigned int *res);
		int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus);
		int snd_hdac_link_power(struct hdac_device *codec, bool enable);

		bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset);

include/sound/hdaudio_ext.h

+0 −12

Original line number	Diff line number	Diff line
		@@ -8,11 +8,6 @@
		*
		* @bus: hdac bus
		* @num_streams: streams supported
		* @ppcap: pp capabilities pointer
		* @spbcap: SPIB capabilities pointer
		* @mlcap: MultiLink capabilities pointer
		* @gtscap: gts capabilities pointer
		* @drsmcap: dma resume capabilities pointer
		* @hlink_list: link list of HDA links
		* @lock: lock for link mgmt
		* @cmd_dma_state: state of cmd DMAs: CORB and RIRB
		@@ -22,12 +17,6 @@ struct hdac_ext_bus {
		int num_streams;
		int idx;

		void __iomem *ppcap;
		void __iomem *spbcap;
		void __iomem *mlcap;
		void __iomem *gtscap;
		void __iomem *drsmcap;

		struct list_head hlink_list;

		struct mutex lock;
		@@ -54,7 +43,6 @@ void snd_hdac_ext_bus_device_remove(struct hdac_ext_bus *ebus);
		#define HDA_CODEC_EXT_ENTRY(_vid, _revid, _name, _drv_data) \
		HDA_CODEC_REV_EXT_ENTRY(_vid, _revid, _name, _drv_data)

		int snd_hdac_ext_bus_parse_capabilities(struct hdac_ext_bus *sbus);
		void snd_hdac_ext_bus_ppcap_enable(struct hdac_ext_bus *chip, bool enable);
		void snd_hdac_ext_bus_ppcap_int_enable(struct hdac_ext_bus *chip, bool enable);

include/uapi/sound/Kbuild

+1 −0

Original line number	Diff line number	Diff line
		@@ -13,3 +13,4 @@ header-y += sb16_csp.h
		header-y += sfnt_info.h
		header-y += tlv.h
		header-y += usb_stream.h
		header-y += snd_sst_tokens.h

include/uapi/sound/snd_sst_tokens.h

0 → 100644

+214 −0

Original line number	Diff line number	Diff line
		/*
		* snd_sst_tokens.h - Intel SST tokens definition
		*
		* Copyright (C) 2016 Intel Corp
		* Author: Shreyas NC <shreyas.nc@intel.com>
		* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License as version 2, as
		* published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful, but
		* WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
		* General Public License for more details.
		*/
		#ifndef __SND_SST_TOKENS_H__
		#define __SND_SST_TOKENS_H__

		/**
		* %SKL_TKN_UUID: Module UUID
		*
		* %SKL_TKN_U8_BLOCK_TYPE: Type of the private data block.Can be:
		* tuples, bytes, short and words
		*
		* %SKL_TKN_U8_IN_PIN_TYPE: Input pin type,
		* homogenous=0, heterogenous=1
		*
		* %SKL_TKN_U8_OUT_PIN_TYPE: Output pin type,
		* homogenous=0, heterogenous=1
		* %SKL_TKN_U8_DYN_IN_PIN: Configure Input pin dynamically
		* if true
		*
		* %SKL_TKN_U8_DYN_OUT_PIN: Configure Output pin dynamically
		* if true
		*
		* %SKL_TKN_U8_IN_QUEUE_COUNT: Store the number of Input pins
		*
		* %SKL_TKN_U8_OUT_QUEUE_COUNT: Store the number of Output pins
		*
		* %SKL_TKN_U8_TIME_SLOT: TDM slot number
		*
		* %SKL_TKN_U8_CORE_ID: Stores module affinity value.Can take
		* the values:
		* SKL_AFFINITY_CORE_0 = 0,
		* SKL_AFFINITY_CORE_1,
		* SKL_AFFINITY_CORE_MAX
		*
		* %SKL_TKN_U8_MOD_TYPE: Module type value.
		*
		* %SKL_TKN_U8_CONN_TYPE: Module connection type can be a FE,
		* BE or NONE as defined :
		* SKL_PIPE_CONN_TYPE_NONE = 0,
		* SKL_PIPE_CONN_TYPE_FE = 1 (HOST_DMA)
		* SKL_PIPE_CONN_TYPE_BE = 2 (LINK_DMA)
		*
		* %SKL_TKN_U8_DEV_TYPE: Type of device to which the module is
		* connected
		* Can take the values:
		* SKL_DEVICE_BT = 0x0,
		* SKL_DEVICE_DMIC = 0x1,
		* SKL_DEVICE_I2S = 0x2,
		* SKL_DEVICE_SLIMBUS = 0x3,
		* SKL_DEVICE_HDALINK = 0x4,
		* SKL_DEVICE_HDAHOST = 0x5,
		* SKL_DEVICE_NONE
		*
		* %SKL_TKN_U8_HW_CONN_TYPE: Connection type of the HW to which the
		* module is connected
		* SKL_CONN_NONE = 0,
		* SKL_CONN_SOURCE = 1,
		* SKL_CONN_SINK = 2
		*
		* %SKL_TKN_U16_PIN_INST_ID: Stores the pin instance id
		*
		* %SKL_TKN_U16_MOD_INST_ID: Stores the mdule instance id
		*
		* %SKL_TKN_U32_MAX_MCPS: Module max mcps value
		*
		* %SKL_TKN_U32_MEM_PAGES: Module resource pages
		*
		* %SKL_TKN_U32_OBS: Stores Output Buffer size
		*
		* %SKL_TKN_U32_IBS: Stores input buffer size
		*
		* %SKL_TKN_U32_VBUS_ID: Module VBUS_ID. PDM=0, SSP0=0,
		* SSP1=1,SSP2=2,
		* SSP3=3, SSP4=4,
		* SSP5=5, SSP6=6,INVALID
		*
		* %SKL_TKN_U32_PARAMS_FIXUP: Module Params fixup mask
		* %SKL_TKN_U32_CONVERTER: Module params converter mask
		* %SKL_TKN_U32_PIPE_ID: Stores the pipe id
		*
		* %SKL_TKN_U32_PIPE_CONN_TYPE: Type of the token to which the pipe is
		* connected to. It can be
		* SKL_PIPE_CONN_TYPE_NONE = 0,
		* SKL_PIPE_CONN_TYPE_FE = 1 (HOST_DMA),
		* SKL_PIPE_CONN_TYPE_BE = 2 (LINK_DMA),
		*
		* %SKL_TKN_U32_PIPE_PRIORITY: Pipe priority value
		* %SKL_TKN_U32_PIPE_MEM_PGS: Pipe resource pages
		*
		* %SKL_TKN_U32_DIR_PIN_COUNT: Value for the direction to set input/output
		* formats and the pin count.
		* The first 4 bits have the direction
		* value and the next 4 have
		* the pin count value.
		* SKL_DIR_IN = 0, SKL_DIR_OUT = 1.
		* The input and output formats
		* share the same set of tokens
		* with the distinction between input
		* and output made by reading direction
		* token.
		*
		* %SKL_TKN_U32_FMT_CH: Supported channel count
		*
		* %SKL_TKN_U32_FMT_FREQ: Supported frequency/sample rate
		*
		* %SKL_TKN_U32_FMT_BIT_DEPTH: Supported container size
		*
		* %SKL_TKN_U32_FMT_SAMPLE_SIZE:Number of samples in the container
		*
		* %SKL_TKN_U32_FMT_CH_CONFIG: Supported channel configurations for the
		* input/output.
		*
		* %SKL_TKN_U32_FMT_INTERLEAVE: Interleaving style which can be per
		* channel or per sample. The values can be :
		* SKL_INTERLEAVING_PER_CHANNEL = 0,
		* SKL_INTERLEAVING_PER_SAMPLE = 1,
		*
		* %SKL_TKN_U32_FMT_SAMPLE_TYPE:
		* Specifies the sample type. Can take the
		* values: SKL_SAMPLE_TYPE_INT_MSB = 0,
		* SKL_SAMPLE_TYPE_INT_LSB = 1,
		* SKL_SAMPLE_TYPE_INT_SIGNED = 2,
		* SKL_SAMPLE_TYPE_INT_UNSIGNED = 3,
		* SKL_SAMPLE_TYPE_FLOAT = 4
		*
		* %SKL_TKN_U32_CH_MAP: Channel map values
		* %SKL_TKN_U32_MOD_SET_PARAMS: It can take these values:
		* SKL_PARAM_DEFAULT, SKL_PARAM_INIT,
		* SKL_PARAM_SET, SKL_PARAM_BIND
		*
		* %SKL_TKN_U32_MOD_PARAM_ID: ID of the module params
		*
		* %SKL_TKN_U32_CAPS_SET_PARAMS:
		* Set params value
		*
		* %SKL_TKN_U32_CAPS_PARAMS_ID: Params ID
		*
		* %SKL_TKN_U32_CAPS_SIZE: Caps size
		*
		* %SKL_TKN_U32_PROC_DOMAIN: Specify processing domain
		*
		* %SKL_TKN_U32_LIB_COUNT: Specifies the number of libraries
		*
		* %SKL_TKN_STR_LIB_NAME: Specifies the library name
		*
		* module_id and loadable flags dont have tokens as these values will be
		* read from the DSP FW manifest
		*/
		enum SKL_TKNS {
		SKL_TKN_UUID = 1,
		SKL_TKN_U8_NUM_BLOCKS,
		SKL_TKN_U8_BLOCK_TYPE,
		SKL_TKN_U8_IN_PIN_TYPE,
		SKL_TKN_U8_OUT_PIN_TYPE,
		SKL_TKN_U8_DYN_IN_PIN,
		SKL_TKN_U8_DYN_OUT_PIN,
		SKL_TKN_U8_IN_QUEUE_COUNT,
		SKL_TKN_U8_OUT_QUEUE_COUNT,
		SKL_TKN_U8_TIME_SLOT,
		SKL_TKN_U8_CORE_ID,
		SKL_TKN_U8_MOD_TYPE,
		SKL_TKN_U8_CONN_TYPE,
		SKL_TKN_U8_DEV_TYPE,
		SKL_TKN_U8_HW_CONN_TYPE,
		SKL_TKN_U16_MOD_INST_ID,
		SKL_TKN_U16_BLOCK_SIZE,
		SKL_TKN_U32_MAX_MCPS,
		SKL_TKN_U32_MEM_PAGES,
		SKL_TKN_U32_OBS,
		SKL_TKN_U32_IBS,
		SKL_TKN_U32_VBUS_ID,
		SKL_TKN_U32_PARAMS_FIXUP,
		SKL_TKN_U32_CONVERTER,
		SKL_TKN_U32_PIPE_ID,
		SKL_TKN_U32_PIPE_CONN_TYPE,
		SKL_TKN_U32_PIPE_PRIORITY,
		SKL_TKN_U32_PIPE_MEM_PGS,
		SKL_TKN_U32_DIR_PIN_COUNT,
		SKL_TKN_U32_FMT_CH,
		SKL_TKN_U32_FMT_FREQ,
		SKL_TKN_U32_FMT_BIT_DEPTH,
		SKL_TKN_U32_FMT_SAMPLE_SIZE,
		SKL_TKN_U32_FMT_CH_CONFIG,
		SKL_TKN_U32_FMT_INTERLEAVE,
		SKL_TKN_U32_FMT_SAMPLE_TYPE,
		SKL_TKN_U32_FMT_CH_MAP,
		SKL_TKN_U32_PIN_MOD_ID,
		SKL_TKN_U32_PIN_INST_ID,
		SKL_TKN_U32_MOD_SET_PARAMS,
		SKL_TKN_U32_MOD_PARAM_ID,
		SKL_TKN_U32_CAPS_SET_PARAMS,
		SKL_TKN_U32_CAPS_PARAMS_ID,
		SKL_TKN_U32_CAPS_SIZE,
		SKL_TKN_U32_PROC_DOMAIN,
		SKL_TKN_U32_LIB_COUNT,
		SKL_TKN_STR_LIB_NAME,
		SKL_TKN_MAX = SKL_TKN_STR_LIB_NAME,
		};

		#endif